TMS320VC33 datasheet(51/59 Pages) TI2

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TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251--1443

timer pin timing

Valid logic-level periods and polarity are specified by the contents of the internal control registers. The following

tables define the timing parameters for the timer pin.

timing requirements for timer pin (see Figure 37 and Figure 38)

VC33-120

VC33-150

UNIT

MIN

MAX

MIN

MAX

UNIT

tsu(TCLK-H1L)†

Setup time, TCLK external before H1 low

th(H1L-TCLK)†

Hold time, TCLK external after H1 low

† These requirements are applicable for a synchronous input clock.

switching characteristics over recommended operating conditions for timer pin (see Figure 37 and

Figure 38)

PARAMETER

VC33-120

VC33-150

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

td(H1H-TCLK)

Delay time, H1 high to TCLK internal

valid

‡

Cycle time TCLK

TCLK ext

tc(H) *2.6

tc(TCLK)‡

Cycle time, TCLK

TCLK int

tc(H) *2

tc(H) *232

tc(H) *2

tc(H) *232

‡

Pulse duration TCLK

TCLK ext

tc(H) +6

tc(H) +5

tw(TCLK)‡

Pulse duration, TCLK

TCLK int

[tc(TCLK)/2] -- 4

[tc(TCLK)/2] + 4

[tc(TCLK)/2] -- 4

[tc(TCLK)/2] + 4

‡ These parameters are applicable for an asynchronous input clock.

TCLK as input

tsu(TCLK-H1L)

th(H1L-TCLK)

tsu(TCLK-H1L)

tw(TCLK)

tc(TCLK)

Figure 37. Timer Pin Timing, Input

TCLK as output

td(H1H-TCLK)

Figure 38. Timer Pin Timing, Output

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