TMS320VC33 datasheet(47/59 Pages) TI2

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TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251--1443

HOLD timing

HOLD is a synchronous input that can be asserted at any time during a clock cycle. If the specified timings are

met, the exact sequence shown in Figure 33 and Figure 34 occurs; otherwise, an additional delay of one clock

cycle is possible.

The table, “timing parameters for HOLD/HOLDA”, defines the timing parameters for the HOLD and HOLDA

signals. The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set,

the device comes out of hold and prevents future hold cycles.

Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a

read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, therefore,

allowing the processor to continue (internally) until a second external write is encountered.

Figure 33, Figure 34, and the accompanying timings are for a zero wait-state bus configuration. Since HOLD

is internally captured by the CPU on the H1 falling edge one cycle before the present cycle is terminated, the

minimum HOLD width for any bus configuration is, therefore, WTCNT+3. Also, HOLD should not be deasserted

before HOLDA has been active for at least one cycle.

timing requirements for HOLD/HOLDA (see Figure 33 and Figure 34)

VC33-120

VC33-150

UNIT

MIN

MAX

MIN

MAX

UNIT

tsu(HOLD-H1L)

Setup time, HOLD before H1 low

tw(HOLD)

Pulse duration, HOLD low

3tc(H)

switching characteristics over recommended operating conditions for HOLD/HOLDA

(see Figure 33 and Figure 34)

PARAMETER

VC33-120

VC33-150

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

tv(H1L-HOLDA)

Valid time, HOLDA after H1 low

--1

tw(HOLDA)

Pulse duration, HOLDA low

2tc(H) -- 4

td(H1L-SH)H

Delay time, H1 low to STRB high for a HOLD

--1

tdis(H1L-S)

Disable time, STRB to the high-impedance state from H1 low

ten(H1L-S)

Enable time, STRB enabled (active) from H1 low

tdis(H1L-RW)

Disable time, R/W to the high-impedance state from H1 low

ten(H1L-RW)

Enable time, R/W enabled (active) from H1 low

tdis(H1L-A)

Disable time, Address to the high-impedance state from H1 low

ten(H1L-A)

Enable time, Address enabled (valid) from H1 low

tdis(H1H-D)

Disable time, Data to the high-impedance state from H1 high

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