UCD3138RMHT datasheet(68/99 Pages) TI2

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11 Power Supply Recommendations

For additonal power supply and layout recommendations, see the UCD3138 Family - Practical Design Guideline

SLUA779

11.1 Introduction To Power Supply and Layout Recommendations

This is an introduction for the sections on Power Supply and Layout.

There are multiple grounds and bias power pins for digital controllers such as the UCD3138 family products.

They are separated from each other because of the digital circuitry and analog circuitry inside the device.

Normally, digital circuits draw more current and generate more noise, but the digital signal is not sensitive to the

noise; while the analog circuit needs quiet power and grounding. A deliberate grounding and power separation

outside the controller can reduce the interference between analog circuits and digital circuits, and therefore, the

controller can have better performance. When they are separated from each other, take care of how the analog

circuit and digital circuit are grouped, respectively, and then how and where they are tied together. With improper

grounding, the device performance can be negatively impacted including DPWM abnormal, device reset, ADC

results, output voltage ripple, and so on.

These sections supersede all older guidelines on UCD family board design and layout. Older EVM designs may

not meet all of these guidelines.

In the PCB design, there are two options. One is to have two separate grounds - digital ground and analog

ground. The other is to use a single ground plane for both digital ground and analog ground. With two separate

ground planes, how to connect digital ground and analog ground is very important, and the PCB must be

designed very carefully. With a single ground plane, there is no concern regarding where two grounds are tied

together, and it makes the PCB design easier. Here, TI recommends using a single ground plane.

In these sections, digital ground is denoted as DGND; analog ground is denoted as AGND; a single ground

plane is denoted as SGND.

11.2 3.3-V Supply Pins

+3.3 V bias normally is produced by a LDO or Buck converter. +5 V (or +12 V) normally are generated by

a flyback converter and it is referenced to the Power Return. A 10 µF capacitor is locally used for LDO or

buck between +3.3 V and Power RTN node. From there, use a single plane (SGND) for both digital ground

and analog ground. A 1Ω resistor is needed between V33D and V33A. V33D and V33DIO should be shorted

externally if they are available and have a wider trace or preferably through its own power plane to connect

them. As an example, a 4.7-µF decoupling capacitor is used for V33A and V33D respectively and these

decoupling capacitors should be placed close to the device pins. In addition, a 10nF capacitor is used for V33A,

V33D and V33DIO respectively to filter out the high frequency noise and placed as close to the pin as possible,

for example the distance is less than 25mils from the capacitor to the pin V33D (or V33DIO) and from the

capacitor to the pin DGND. 10 nF uses smaller package such as 0402 and low ESR capacitor. Refer to the

Layout section. There should not be any voltage delta between the DGND pins and AGND pins. Multiple vias

are required to connect the extended power pad (for example, copper plane under the device power pad) to

the internal single ground (SGND) plane layer. All digital and analog ground pins are directly connected to the

extended power pad and connected to the internal SGND plane through vias.

11.3 Recommendation for V33 Ramp up Slew Rate for UCD3138 and UCD3138064

UCD3138 and UCD3138064 need a 2.2-µF pullup capacitor from BP18 to V33 as described before. Capacitors

with a value of 2.2 µF and 1 µF create a capacitor divider which pull BP18 up as V33 rises. Ensure that as V33

rises, the slew rate is not fast enough to cause BP18 to overshoot, resulting in a reliability issue. TI requires that

the maximum voltage of BP18 does not exceed 1.95 V. By calculation, if V33 ramps up linearly, the maximum

V33 slew rate should be less than 6 V/ms.

Also, the internal BP18 regulator is enabled when V33 is higher than VGH and POR is activated. V33 charges the

capacitor of BP18 through the internal regulator. This charge causes a voltage dip in the V33 pin as shown in

Figure 11-1 and the charge may trigger a V33 undervoltage (POR) event, causing a chip reset. To prevent POR

trigger signal oscillation and successive chip resets, TI recommends a minimum slew rate of 2.6 V/ms.

UCD3138

SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021

www.ti.com

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