UCD3138RMHT datasheet(24/99 Pages) TI2

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This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz each. The

high resolution section of DPWM can be enabled or disabled, also the resolution can be defined in several steps

between 4ns to 250ps. This is done by setting the values of PWM_HR_MULTI_OUT_EN, HIRES_SCALE, and

ALL_PHASE_CLK_ENA inside the DPWM Control register 1. See the Power Peripherals programmer’s manual

for details.

8.8.1.5 Oversampling

The DPWM module has the capability to trigger an oversampling event by initiating the EADC to sample the

error voltage. The default 00 configuration has the DPWM trigger the EADC once based on the sample trigger

Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the sampling register. The 01

setting triggers 2X oversampling, the 10 setting triggers 4X over sampling, and the 11 triggers oversampling at

8X.

8.8.1.6 DPWM Interrupt Generation

The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in the

period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower interrupt

service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12 trigger for

sequence synchronization. Table 8-3 outlines the divide ratios that can be programmed.

8.8.1.7 DPWM Interrupt Scaling/Range

Table 8-3. DPWM Interrupt Divide Ratio

Interrupt Divide

Setting

Interrupt Divide

Count

Interrupt Divide

Count (hex)

Switching Period

Frames (Assume 1-MHz

Loop)

Number of 32-MHz

Processor Cycles

128

256

512

1024

1536

2048

2560

3072

127

128

4096

159

160

5120

191

192

6144

223

224

7168

255

256

8192

UCD3138

SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021

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