MS85RC1MTY(AEC-Q100 Compliant)

8

DS501-00095-0v1-E

• Current Address Read

When the previous write or read operation finishes successfully up to the stop condition, the memory address

accessed last time is remain in memory address buffer(17bits). As it is, then send the command without

turning off the power, the memory address "n", total 17 bits consist of the 1 bit of the top memory address

from the Device Address Word input and lower 16 bits of memory address buffer, is read from the address

"n+1". If the memory address “n” is last address, the address counter will roll over to (0000H). The current

address in memory address buffer is undefined immediately after the power is turned on.

• Random Read

The one byte of data from the memory address saved in the memory address buffer can be read out

synchronously to SCL by specifying the address in the same way as for a write, and then issuing another

start condition and sending the Device Address Word (R/W “1” input). The top address input at second time

need to same value as top address inputed first time. If input the different value at first time and second time,

the second value is reflected as the address to access. The final NACK (SDA is the “H” level) is issued by

the receiver that receives the data. In this case, this bit is issued by the master side.

A

S

P

N

S

A2 A1

A

N P

Read

Data 8bits

1

1

010

A16

Access from master

Access from slave

Start Condition

ACK(SDA is the “L” level)

Stop Condition

NACK(SDA is the “H” level)

Address n+1

A

S

P

N

S

A2 A1

A

A

A

P

Address

High 8bits

Address

Low 8bits

0

1 010

S

A2 A1

A

1

1 010

Read

Data 8bits

N

A16

A16

Access from master

Access from slave

Start Condition

ACK(SDA is the “L” level)

Stop Condition

NACK(SDA is the “H” level)