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AECLKOUT

ACEx

ABE[7:0]

AEA[19:0]/

ABA[1:0]

AED[63:0]

AAOE/ASOE(A)

AR/W

AAWE/ASWE(A)

AARDY(B)

ByteEnables

Address

ReadData

Hold=1

Strobe=4

Setup=1

DEASSERTED

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372A – MAY 2007 – REVISED JUNE 2007

Table 6-32. Switching Characteristics Over Recommended Operating Conditions for Asynchronous

Memory Cycles for EMIFA Module(1)(2)(3) (see Figure 6-15 and Figure 6-16)

-720

-900

NO.

PARAMETER

UNIT

MIN

MAX

tosu(SELV-AOEL)

Output setup time, select signals valid to AAOE low

RS * E – 1.5

toh(AOEH-SELIV)

Output hold time, AAOE high to select signals invalid

RS * E – 1.9

td(EKOH-AOEV)

Delay time, AECLKOUT high to AAOE valid

tosu(SELV-AWEL)

Output setup time, select signals valid to AAWE low

WS * E – 1.7

toh(AWEH-SELIV)

Output hold time, AAWE high to select signals invalid

WH * E – 1.8

td(EKOH-AWEV)

Delay time, AECLKOUT high to AAWE valid

1.3

7.1

(1)

E = AECLKOUT period in ns for EMIFA

(2)

RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters

are programmed via the EMIFA CE Configuration registers (CEnCFG).

(3)

Select signals for EMIFA include: ACEx, ABE[7:0], AEA[19:0], ABA[1:0]; and for EMIFA writes, also include AR/W, AED[63:0].

AAOE /ASOE and AAWE ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during

asynchronous memory accesses.

Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration

Figure 6-15. Asynchronous Memory Read Timing for EMIFA

Peripheral Information and Electrical Specifications

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