TMS320DM647 datasheet(5/167 Pages) TI

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Contents

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372A – MAY 2007 – REVISED JUNE 2007

TMS320DM647/TMS320DM648 Digital Media

Peripheral Information and Electrical

Processor

.................................................. 1

Specifications

........................................... 55

1.1

Features

.............................................. 1

6.1

Parameter Information

.............................. 55

6.2

Recommended Clock and Control Signal Transition

1.1.1

Trademarks

.......................................... 2

Behavior

............................................. 57

1.2

Description

............................................ 2

6.3

Power Supplies

...................................... 57

1.3

Functional Block Diagram

............................ 4

6.4

PLL1 and PLL1 Controller

........................... 62

Device Overview

......................................... 6

6.5

PLL2 and PLL2 Controller

........................... 65

2.1

Device Characteristics

................................ 6

6.6

Enhanced Direct Memory Access (EDMA3)

2.2

CPU (DSP Core) Description

......................... 7

Controller

............................................ 68

2.3

C64x+ CPU

.......................................... 10

6.7

Reset Controller

..................................... 81

2.4

Memory Map Summary

............................. 12

6.8

Interrupts

............................................ 88

2.5

Pin Assignments

.................................... 15

6.9

DDR2 Memory Controller

........................... 92

2.6

Terminal Functions

.................................. 19

6.10

External Memory Interface A (EMIFA)

.............. 94

2.7

Device Support

...................................... 33

6.11

Video Port

.......................................... 102

2.8

Device and Development-Support Tool

6.12

VCXO Interpolated Control (VIC)

.................. 110

Nomenclature

....................................... 34

6.13

Universal Asynchronous Receiver/Transmitter

2.9

Documentation Support

............................. 35

(UART)

............................................. 112

Device Configuration

.................................. 37

6.14

Inter-Integrated Circuit (I2C)

....................... 114

3.1

System Module Registers

........................... 37

6.15

Host-Port Interface (HPI) Peripheral

............... 118

3.2

Bootmode Registers

................................ 37

6.16

Peripheral Component Interconnect (PCI)

......... 129

3.3

Debugging Considerations

.......................... 46

6.17

Multichannel Audio Serial Port (McASP)

3.4

Pullup/Pulldown Resistors

........................... 46

Peripheral

.......................................... 134

System Interconnect

................................... 48

6.18

3-Port Ethernet Switch Subsystem (3PSW)

....... 142

4.1

Internal Buses, Bridges, and Switch Fabrics

........ 48

6.19

Management Data Input/Output (MDIO)

........... 151

4.2

Data Switch Fabric Connections

.................... 48

6.20

Timers

.............................................. 153

4.3

Configuration Switch Fabric

......................... 50

6.21

VLYNQ Peripheral

................................. 155

Device Operating Conditions

........................ 52

6.22

General-Purpose Input/Output (GPIO)

............. 158

5.1

Absolute Maximum Ratings Over Operating

6.23

IEEE 1149.1 JTAG

................................. 161

Temperature Range (Unless Otherwise Noted)

..... 52

Mechanical Data

....................................... 163

5.2

Recommended Operating Conditions

............... 53

7.1

Thermal Data for ZUT

.............................. 163

5.3

Electrical Characteristics Over Recommended

7.1.1

Packaging Information

............................. 163

Ranges of Supply Voltage and Operating

Temperature (Unless Otherwise Noted)

............ 54

Revision History

............................................ 164

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