 |
Os motores de busca de Datasheet de Componentes eletrônicos |
|
|
Os motores de busca de Datasheet de Componentes eletrônicos |
|
TMS320DM647 Folha de dados(PDF) 39 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TMS320DM647 Folha de dados(HTML) 39 Page - Texas Instruments |
|
|
39 / 167 page  www.ti.com 3.2.3 Boot Complete (BOOTCMPLT) register 3.2.4 Priority Allocation (PRI_ALLOC) TMS320DM647/TMS320DM648 Digital Media Processor SPRS372A – MAY 2007 – REVISED JUNE 2007 Figure 3-2. DSPBOOTADDR Register 31 10 9 0 BOOTADDR Reserved R/W-0100 0010 0010 0000 0000 00 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-3. DSPBOOTADDR Register Field Descriptions Bit Field Value Description 31:10 BOOTADDR Upper 22 bits of the C64x+ DSP bootmode address 9:0 Reserved Reserved The BOOTCMPLT register contains a BC (boot complete) field in bit 0, and a ERR (boot error) field in bits 19:16. The BC field is written by the external host to indicates that it has completed boot. In the bootloader code, the CPU can poll for this bit. Once this bit = 1, the CPU can begin executing from DSPBOOTADDR. The ERR field is written by the bootloader software if the software detects a boot error. Coming out of a boot, application software can read this field to determine if boot was accomplished. Actual error code is determined by software. Figure 3-3. BOOTCMPLT Register 3 31 20 19 16 15 1 0 Reserved ERR Reserved B C R-0 R-0 R-0 R- 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-4. BOOTCMPLT Register Field Descriptions Bit Field Value Description 31:20 Reserved Reserved 19:16 ERR Boot error 0000 No error 0001 – 1111 Bootloader software detected boot error. For details on boot errors, see the Using the TMS320DM647x Bootloader Application Note (literature number SPRAAAJ1). 15:1 Reserved Reserved 0 BC Boot Complete Flag from host. This is applicable only to host boots. 0 Host has not completed booting this device. 1 Host has completed booting this device and the DSP can begin executing from DSPBOOTADDR. Each of the masters (excluding the C64x+ Megamodule) is assigned a priority via the Priority Allocation Register (PRI_ALLOC), see Figure 3-4. The priority is enforced when several masters in the system are vying for the same endpoint. A value of 000b has the highest priority, while 111b has the lowest priority. Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will be enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the C64x+ Megamodule. Submit Documentation Feedback Device Configuration 39 |
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Portuguese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
