WM8994ECSSLASHR datasheet(186/363 Pages) CIRRUS

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WM8994

186

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R785 (0311h)

AIF2 Control

(2)

AIF2DACL_

SRC

AIF2 Left Receive Data Source Select

0 = Left DAC receives left interface data

1 = Left DAC receives right interface data

AIF2DACR_

SRC

AIF2 Right Receive Data Source Select

0 = Right DAC receives left interface data

1 = Right DAC receives right interface data

AIF2DAC_T

AIF2 receive (DAC) TDM Enable

0 = Normal DACDAT2 operation

1 = TDM enabled on DACDAT2

AIF2DAC_T

DM_CHAN

AIF2 receive (DAC) TDM Slot Select

0 = Slot 0

1 = Slot 1

11:10

AIF2DAC_B

OOST [1:0]

AIF2 Input Path Boost

00 = 0dB

01 = +6dB (input must not exceed -6dBFS)

10 = +12dB (input must not exceed -12dBFS)

11 = +18dB (input must not exceed -18dBFS)

R790 (0316h)

AIF2 DAC

Data

AIF2DACL_

DAT_INV

AIF2 Left Receive Data Invert

0 = Not inverted

1 = Inverted

AIF2DACR_

DAT_INV

AIF2 Right Receive Data Invert

0 = Not inverted

1 = Inverted

R791 (0317h)

AIF2 ADC

Data

AIF2ADCL_

DAT_INV

AIF2 Left Transmit Data Invert

0 = Not inverted

1 = Inverted

AIF2ADCR_

DAT_INV

AIF2 Right Transmit Data Invert

0 = Not inverted

1 = Inverted

Table 98 AIF2 Digital Audio Data Control

AIF2 - MONO MODE

AIF2 can be configured to operate in mono DSP mode by setting AIF2_MONO = 1 as described in

Table 99. Note that mono mode is only supported in DSP mode, ie when AIF2_FMT = 11.

In mono mode, the Left channel data or the Right channel data may be selected for output on

ADCDAT2. The selected channel is determined by the AIF2ADCL_ENA and AIF2ADCR_ENA bits. (If

both bits are set, then the Right channel data is selected.)

In mono mode, the DACDAT2 input can be enabled on the Left and/or Right signal paths using the

AIF2DACL_ENA and AIF2DACR_ENA bits. The mono input can be enabled on both paths at the

same time if required.

In mono mode, the number of BCLK cycles per LRCLK frame must be less than double the AIF2 word

length. This requires AIF2DAC_RATE to be less than double the value selected by the AIF2_WL

than double the value selected by the AIF2_WL register. See Table 89 for details of the

AIF2DAC_RATE and AIF2ADC_RATE registers.

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