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WM8994ECS/R Folha de dados(PDF) 184 Page - Cirrus Logic

Nome de Peças WM8994ECS/R
Descrição Electrónicos  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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Fabricante Electrônico  CIRRUS [Cirrus Logic]
Página de início  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8994ECS/R Folha de dados(HTML) 184 Page - Cirrus Logic

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WM8994
184
Rev 4.6
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R787 (0313h)
AIF2 BCLK
8:4
AIF2_BCLK
_DIV [4:0]
00100
BCLK2 Rate
00000 = AIF2CLK
00001 = AIF2CLK / 1.5
00010 = AIF2CLK / 2
00011 = AIF2CLK / 3
00100 = AIF2CLK / 4
00101 = AIF2CLK / 5
00110 = AIF2CLK / 6
00111 = AIF2CLK / 8
01000 = AIF2CLK / 11
01001 = AIF2CLK / 12
01010 = AIF2CLK / 16
01011 = AIF2CLK / 22
01100 = AIF2CLK / 24
01101 = AIF2CLK / 32
01110 = AIF2CLK / 44
01111 = AIF2CLK / 48
10000 = AIF2CLK / 64
10001 = AIF2CLK / 88
10010 = AIF2CLK / 96
10011 = AIF2CLK / 128
10100 = AIF2CLK / 176
10101 = AIF2CLK / 192
10110 - 11111 = Reserved
R788 (0314h)
AIF2ADC
LRCLK
11
AIF2ADC_L
RCLK_DIR
0
Allows ADCLRCLK2 to be enabled in Slave
mode
0 = Normal
1 = ADCLRCLK2 enabled in Slave mode
10:0
AIF2ADC_R
ATE [10:0]
040h
ADCLRCLK2 Rate
ADCLRCLK2 clock output =
BCLK2 / AIF2ADC_RATE
Integer (LSB = 1)
Valid from 8..2047
R789 (0315h)
AIF2DAC
LRCLK
11
AIF2DAC_L
RCLK_DIR
0
Allows LRCLK2 to be enabled in Slave mode
0 = Normal
1 = LRCLK2 enabled in Slave mode
10:0
AIF2DAC_R
ATE [10:0]
040h
LRCLK2 Rate
LRCLK2 clock output =
BCLK2 / AIF2DAC_RATE
Integer (LSB = 1)
Valid from 8..2047
Table 97 AIF2 BCLK and LRCLK Control



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