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WM8994ECS/R Folha de dados(PDF) 34 Page - Cirrus Logic |
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WM8994ECS/R Folha de dados(HTML) 34 Page - Cirrus Logic |
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34 / 363 page  WM8994 34 Rev 4.6 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCKS & FREQUENCY LOCKED LOOP (FLL) MCLK tMCLKL tMCLKH tMCLKY VIH VIL Figure 2 Master Clock Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Master Clock Timing (MCLK1 and MCLK2) MCLK cycle time TMCLKY MCLK as input to FLL, FLLn_REFCLK_DIV = 01, 10, 11 37 ns MCLK as input to FLL, FLLn_REFCLK_DIV = 00 74 FLL not used, AIFnCLK_DIV = 1 40 FLL not used, AIFnCLK_DIV = 0 80 MCLK duty cycle (= TMCLKH : TMCLKL) 60:40 40:60 Frequency Locked Loops (FLL1 and FLL2) FLL Input Frequency FLLn_REFCLK_DIV = 00 0.032 13.5 MHz FLLn_REFCLK_DIV = 01 0.064 27 FLLn_REFCLK_DIV = 10 0.128 27 FLLn_REFCLK_DIV = 11 0.256 27 Internal Clocking AIF1CLK frequency 12.5 MHz AIF2CLK frequency 12.5 MHz SYSCLK frequency 12.5 MHz |
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