| Os motores de busca de Datasheet de Componentes eletrônicos |
|
WM8994ECS/R Folha de dados(PDF) 185 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
WM8994ECS/R Folha de dados(HTML) 185 Page - Cirrus Logic |
|
185 / 363 page ![]() WM8994 Rev 4.6 185 AIF2 - DIGITAL AUDIO DATA CONTROL The register bits controlling the audio data format, word length, left/right channel selection and TDM control for AIF2 are described in Table 98. When TDM mode is enabled on AIF2, the WM8994 can transmit and receive audio data in Slot 0 or Slot 1. In this case, the ADCDAT2 output is tri-stated during the unused timeslot, allowing another device to transmit data on the same pin. See “Signal Timing Requirements” for the associated timing details. (Note that, when TDM is not enable d on AIF2, the ADCDAT2 output is driven logic ‘0’ during the unused timeslot.) In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK following a rising edge of LRCLK (assuming default BCLK polarity). This is selected using the AIF2_LRCLK_INV register bit, as described in Table 97. A digital gain function is available at the audio interface input path to boost the DAC volume when a small signal is received on DACDAT2. This is controlled using the AIF2DAC_BOOST register. To prevent clipping, this function should not be used when the boosted data is expected to be greater than 0dBFS. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R784 (0310h) AIF2 Control (1) 15 AIF2ADCL_ SRC 0 AIF2 Left Digital Audio interface source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 14 AIF2ADCR_ SRC 1 AIF2 Right Digital Audio interface source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel 13 AIF2ADC_T DM 0 AIF2 transmit (ADC) TDM Enable 0 = Normal ADCDAT2 operation 1 = TDM enabled on ADCDAT2 12 AIF2ADC_T DM_CHAN 0 AIF2 transmit (ADC) TDM Slot Select 0 = Slot 0 1 = Slot 1 6:5 AIF2_WL [1:0] 10 AIF2 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Note - 8-bit modes can be selected using the “Companding” control bits. 4:3 AIF2_FMT [1:0] 10 AIF2 Digital Audio Interface Format 00 = Right justified 01 = Left justified 10 = I2S Format 11 = DSP Mode |
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |