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SPSB100 Folha de dados(PDF) 35 Page - STMicroelectronics

Nome de Peças SPSB100
Descrição Electrónicos  Automotive power management IC for highly integrated processors
PDF  214 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPSB100 Folha de dados(HTML) 35 Page - STMicroelectronics

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3.7
Power-up and power-down sequence
Power-up and power-down sequences turn ON and OFF all the regulators automatically. The sequences are
executed by the device state machine as described in the Section 3.6: Functional overview - State machine and
are fully programmable through the USER-NVM space to cover a broad range of applications.
The sequences control BUCK1, 2, 3 and LDO1, 2 regulators, together with NRST pin.
3.7.1
Power-up sequence
Power-up sequence is made of 7 steps as described below.
Figure 22. Power-up sequence
Step #N:
Turn ON regulators & deassert NRESET (*) if
their PU_STEP_ON (resp
PU_STEP_DEASSERT ) = N,
no action on others.
Start
(At least one regulator has
been turned ON) AND
(PU_WAIT_PG_ON <N> = 1)
?
Start TimeOut counter,
wait regulators PG signal
of just turned ON
regulators
Y
N
Wait for
PU_WAIT_DEL_ON <N> ms
Set N = N + 1
N ≥ 8 ?
Y
N
Set PUretry = 0
Finished OK
INIT
state
PG OK before
TimeOut
TimeOut
reached
Execute Power -
Down sequence
Set PUretry =
PUretry + 1
(PUretry ≤
3) OR
(PU_LOOP
_FOR_EV
ER = 1) ?
N
Power-Up sequence
Power-Up retry loop
set N=1
End
Wait 100ms
End
Retry loop
failed
Set PUretry = 0
Set PUretry = 0
NVM-DL
REGfail & GoREC=1 on
any enabled regulator
Safety checks OK
AND VFBB_OK_R < VFBB < VFBB_OV
Each of BUCK-1, -2, -3, and LDO-1, -2 can be turned ON with USER-NVM bits BUCK1_PU_STEP_ENA,
BUCK2_PU_STEP_ENA, BUCK3_PU_STEP_ENA, LDO1_PU_STEP_ENA, LDO2_PU_STEP_ENA at any step
from 1 to 7. None, or more than one regulator can be turned ON at a step.
The NRST pin can be deasserted at any step from 1 to 7, with USER-NVM bits NRESET_PU_STEP_DEASSERT
independently of regulators setting. Note that the watchdog time-out starts at the step where NRST is deasserted.
After a regulator has been turned ON at step N the sequence offers the possibility to wait for power-good signal
with USER-NVM bits PU_WAIT_PG_ENA_X (X equal to steps from 1 to 7):
SPSB100
Functional description
DS14640 - Rev 1
page 35/214



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