SPSB100 datasheet(21/214 Pages) STMICROELECTRONICS

21 / 214 page

Note:

After the first power up is needed to align the live bit associated in DSR18 (LDO1_ENA_STATUS) with the

current value associated in DCR1.

•

Power-good used to signal LDO1 power on success (flag is LDO1_PG_OK bit):

–

If not, after TLDO1_PG_TO timing, LDO1 is switched off and flag LDO1_PG_TIMEOUT is set.

•

The power on success generates an IRQ except if it is masked with MASK_LDO1_PG_IRQ.

•

Not successful power-good detection generates an IRQ except if MASK_LDO1_PG_TIMEOUT_IRQ is set.

•

After a fault detection (UV or PG timeout), LDO1 can be re

‑enabled by setting LDO1_ENA = 0 followed by

LDO1_ENA = 1, even if fail flags are not cleared.

Current limitation ILDO1_Cmax of the regulator ensures fast charge of external decoupling capacitors.

The output voltage is stable for ceramic load capacitors CLDO1_load ≥ 1 µF.

Warning temperature detection by a local thermal sensor (flag is TW_CL0).

Warning temperature detection generates an IRQ except if MASK_CL0_TW_IRQ is set.

In case the device temperature exceeds the TSD_CL0 threshold, the device executes a power down sequence

before entering in REC-2 state.

3.4.2

LDO2

The SPSB100 embeds one low dropout tracking regulator designed to provide an output voltage that closely

tracks bucks reference at ±10 mV while delivering on the LDO2 output pin up to 10 mA. The LDO2 voltage tracker

is supplied by pin FBB.

LDO2_ENA SPI bit is used to enable/disable this LDO (only after SPI_PROTECT_ACCESS has been set. LDO2

must be disabled before entering in active low power mode and must not be enabled in this mode).

LDO2 can be configured by means of the USER-NVM LDO2_TRK bits to track one of BUCK1, BUCK2 or BUCK3

if related output voltages are 5 V or 3.3 V (see the Table 6).

Table 6. Voltage regulators configuration

Tracking

configuration

LDO2_TRK[0,1] USER-

NVM configuration bits

Selected voltage

source

Source output voltage

LDO2 behavior

BUCK1

3.3 V or 5 V

Tracks buck1

6.5 V

OFF what ever LDO2_ENA

BUCK2

3.3 V or 5 V

Tracks buck2

6.5 V

OFF what ever LDO2_ENA

BUCK3

0.98 V ÷ 1.25 V

OFF what ever LDO2_ENA

3.3 V

Tracks buck3

LDO2 is supplied by FBB.

The tracking regulator is protected against:

•

The live bit LDO2_ENA_STATUS reflects the state of LDO2 output.

Note:

After the first power-up is needed to align the live bit associated in DSR18 (LDO2_ENA_STATUS) with

the current value associated in DCR1.

•

Overvoltage detection to monitor the output voltage (flag is LDO2_OV bit) and LDO2 is therefore switched

off.

•

Overvoltage detection generates an IRQ except if MASK_LDO2_IRQ is set.

•

Undervoltage detection (the flag is LDO2_UV bit) and LDO2 are therefore switched off.

•

Undervoltage detection generates an IRQ except if MASK_LDO2_IRQ is set.

•

Power-good used to signal LDO2 power on success (flag is LDO2_PG_OK bit).

•

If not, after TLDO2_PG_TO timing, LDO2 is switched off and flag LDO2_PG_TIMEOUT is set.

•

The power-on success generates an IRQ except if it is masked with MASK_LDO2_PG_IRQ.

•

Not successful power-good detection generates an IRQ except if MASK_LDO2_PG_TIMEOUT_IRQ is set.

•

Warning temperature detection by a local thermal sensor(flag is TW_CL4).

•

Warning temperature detection generates an IRQ except if MASK_CL4_TW_IRQ is set.

SPSB100

Functional description

DS14640 - Rev 1

page 21/214

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