ADIN1100CCPZ-R7 datasheet(75/80 Pages) AD

75 / 80 page

Data Sheet

ADIN1100

analog.com

Rev. B | 75 of 80

Table 128. Bit Descriptions for FC_USZ_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_USZ_CNT

Latched Copy of the Undersized Frame Error Counter.

0x0

Frame Checker Odd Nibble Frame Count Register

Device Address: 0x1F; Register Address: 0x8010, Reset: 0x0000, Name: FC_ODD_CNT

This register is a latched copy of the odd nibble frame register. This register is a count of received frames with an odd number of nibbles in the

frame. When the receive error counter (RX_ERR_CNT) is read, the odd nibble frame counter register is latched, which ensures that the odd

nibble frame count and the receive frame count are synchronized.

Table 129. Bit Descriptions for FC_ODD_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_ODD_CNT

Latched Copy of the Odd Nibble Counter.

0x0

Frame Checker Odd Preamble Packet Count Register

Device Address: 0x1F; Register Address: 0x8011, Reset: 0x0000, Name: FC_ODD_PRE_CNT

This register is a latched copy of the odd preamble packet counter register. This register is a count of received packets with an odd number of

nibbles in the preamble. When the receive error counter (RX_ERR_CNT) is read, the odd preamble packet counter register is latched, which

ensures that the odd preamble packet count and the receive frame count are synchronized.

Table 130. Bit Descriptions for FC_ODD_PRE_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_ODD_PRE_CNT

Latched Copy of the Odd Preamble Packet Counter.

0x0

Frame Checker False Carrier Count Register

Device Address: 0x1F; Register Address: 0x8013, Reset: 0x0000, Name: FC_FALSE_CARRIER_CNT

This register is a latched copy of the false carrier events counter register. This register is a count of the number of times the bad SSD state

is entered. When the receive error counter (RX_ERR_CNT) is read, the false carrier events counter register is latched, which ensures that the

false carrier events count and the receive frame count are synchronized.

Table 131. Bit Descriptions for FC_FALSE_CARRIER_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_FALSE_CARRIER_CNT

Latched Copy of the False Carrier Events Counter.

0x0

Frame Generator Enable Register

Device Address: 0x1F; Register Address: 0x8020, Reset: 0x0000, Name: FG_EN

This register is used to enable the frame generator. When the frame generator is enabled, the source of data for the PHY comes from the frame

generator and not the MAC interface.

Table 132. Bit Descriptions for FG_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FG_EN

Frame Generator Enable.

0x0

R/W

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