ADIN1100CCPZ-R7 datasheet(51/80 Pages) AD

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Data Sheet

ADIN1100

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Rev. B | 51 of 80

Table 55. Bit Descriptions for B10L_PMA_CNTRL (Continued)

Bits

Bit Name

Description

Reset

Access

[9:1]

RESERVED

Reserved.

0x0

B10L_LB_PMA_LOC_EN

10BASE-T1L PMA Loopback. When this bit is set to 1, the PMA accepts data on the transmit

path and returns it on the receive path. When this bit is set to 0, the PMA works in normal

mode.

0x0

R/W

10BASE-T1L PMA Status Register

Device Address: 0x01; Register Address: 0x08F7, Reset: 0x2800, Name: B10L_PMA_STAT

This address corresponds to the 10BASE-T1L PMA status register specified in Clause 45.2.1.186b of Standard 802.3cg.

Table 56. Bit Descriptions for B10L_PMA_STAT

Bits

Bit Name

Description

Reset

Access

[15:14]

RESERVED

Reserved.

0x0

B10L_LB_PMA_LOC_ABLE

10BASE-T1L PMA Loopback Ability. This bit always reads as 1 because the PMA has

loopback ability.

0x1

B10L_TX_LVL_HI_ABLE

10BASE-T1L High Voltage Transmit Ability. Indicates that the PHY supports 10BASE-

T1L high voltage (2.4 V p-p) transmit level operating mode.

Pin dependent

B10L_PMA_SFT_PD_ABLE

PMA Supports Power-Down. Indicates that the PMA supports software power-down.

0x1

B10L_EEE_ABLE

10BASE-T1L EEE Ability. Indicates if the PHY supports 10BASE-T1L EEE.

0x0

[9:0]

RESERVED

Reserved.

0x0

10BASE-T1L Test Mode Control Register

Device Address: 0x01; Register Address: 0x08F8, Reset: 0x0000, Name: B10L_TEST_MODE_CNTRL

This address corresponds to the 10BASE-T1L PMA test mode control register specified in Clause 45.2.1.186c of Standard 802.3cg. The default

value of this register selects normal operation without management intervention as the initial state of the device.

Table 57. Bit Descriptions for B10L_TEST_MODE_CNTRL

Bits

Bit Name

Description

Reset

Access

[15:13]

B10L_TX_TEST_MODE

10BASE-T1L Transmitter Test Mode.

0x0

R/W

000: normal operation.

001: Test Mode 1—transmitter output voltage and timing jitter test mode. When Test Mode 1 is

enabled, the PHY repeatedly transmits the data symbol sequence (+1, −1).

010: Test Mode 2—transmitter output droop test mode. When Test Mode 2 is enabled, the PHY

transmits ten +1 symbols followed by ten −1 symbols.

011: Test Mode 3—normal operation in idle mode. When Test Mode 3 is enabled, the PHY transmits

as in nontest operation and in the master data mode with data set to normal interframe idle signals.

[12:0]

RESERVED

Reserved.

0x0

10BASE-T1L PMA Link Status Register

Device Address: 0x01; Register Address: 0x8302, Reset: 0x0000, Name: B10L_PMA_LINK_STAT

This address can be read to determine the 10BASE-T1L PMA link status. Reading B10L_PMA_LINK_STAT clears the latching condition of the

bits in Table 58.

Table 58. Bit Descriptions for B10L_PMA_LINK_STAT

Bits

Bit Name

Description

Reset

Access

[15:10]

RESERVED

Reserved.

0x0

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