ADIN1100CCPZ-R7 datasheet(36/80 Pages) AD

36 / 80 page

Data Sheet

ADIN1100

APPLICATIONS INFORMATION

analog.com

Rev. B | 36 of 80

Note that during normal operation, a 25 MHz reference clock

generated from the external clock source input (crystal, 25 MHz or

50 MHz clock) is provided on the CLK25_REF output pin. This pin

can be used as a reference clock for other circuits, such as another

10BASE-T1L device. CLK25_REF is disabled in reset mode.

External Crystal Oscillator for RMII and RGMII

Modes

The typical connection for an external crystal (XTAL) is shown in

Figure 23.

To ensure minimum current consumption and to minimize stray

capacitance, make connections between the crystal, capacitors,

and ground as close to the ADIN1100 as possible. Consult individ-

ual crystal vendors for recommended load information and crystal

performance specifications.

The crystal load capacitance (CL) is defined by the crystal ven-

dor. CPCB1 and CPCB2 are the parasitic capacitance between the

XTAL_I/CLK_IN and XTAL_O tracks and the ground plane beneath,

respectively. CX1 and CX2 are the two external load capacitors

required for the oscillator to operate.

Assuming the following:

►

CPCB1 ≈ CPCB2 ≈ CPCBx

►

CX1 ≈ CX2 ≈ CXx

Then, CXx = 2 × CL – CPCBx – 3 pF

Choose precision capacitors for CXx with low appreciable tempera-

ture coefficient to minimize frequency errors.

To ensure minimum current consumption and to minimize stray

capacitance, make the connections between the crystal, capacitors,

and ground as close to the ADIN1100 as possible.

Figure 23. Crystal Oscillator Connection

External 25 MHz Clock Input for MII and RGMII

Modes

A single-ended 25 MHz reference clock on XTAL_I/CLK_IN can be

used for MII or RGMII mode. The clock source must be dc-coupled

with the ADIN1100 XTAL_I/CLK_IN pin input, and the XTAL_O pin

must be left open circuit.

With 0.8 V ≤ VCLK_IN p-p ≤ 2.5 V, the following results:

►

For 0.8 V ≤ VS p-p ≤ 1.0 V, the following is true:

►

R1 = 50 Ω

►

R2 is not required

►

For 1.0 V < VS p-p < 1.8 V, the following is true:

►

For best performance, set VCLK_IN to 1.0 V p-p

►

500 Ω ≤ R1 ≤ 2 kΩ

►

1 kΩ ≤ R2 ≤ 2 kΩ

►

VS p-p – VCLK_IN p-p > 0.2 V

►

R2 = VCLK_IN p−p × R1

VS p−p− VCLK_IN p−p

►

For 1.8 V ≤ VS p-p, the following is true:

►

R1 = 2 kΩ

►

R2 = 2 kΩ

Figure 24. External 25 MHz Clock Input Circuit for MII and RGMII Modes

Table 27. R1 and R2 Values for Different VS p-p Values with VCLK_IN = 1 V p-p

VS (V p-p)

1.0

50 Ω

Not applicable

1.2

500 Ω

2.5 kΩ

1.8

2 kΩ

2.2

2 kΩ

2.5

2 kΩ

2.8

2 kΩ

3.0

2 kΩ

3.3

2 kΩ

External 50 MHz Clock Input for RMII Mode

RMII mode requires a single-ended 50 MHz reference clock signal

on XTAL/CLK_IN with the XTAL_O pin left open circuit.

The PCB parasitic impedance requires particular attention, and it

is recommended to match the clock trace lengths between the

ADIN1100 and the external MAC (for example, the meandered

trace) for RMII timing purposes.

ADIN1100CCPZ-R7 Folha de dados(PDF) 36 Page - Analog Devices

ADIN1100CCPZ-R7 Folha de dados(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Folha de dados Download

Ligação URL