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AS7331

Functional Description

Datasheet

• PUBLIC

DS001047

• v4-00 • 2023-Mar-24

│ 31

Where:

MRES = Digital output value of the conversion (content of output registers MRES1 to MRES3).

Ee =

Input light irradiance regarding to the photodiode’s area within the conversion time interval.

FSREe = Full Scale Range of detectable input light irradiance Ee.

Re = Irradiance responsivity (see Figure 12).

TCONV = Conversion time interval.

NCLK = Number of clock cycles within the conversion time interval TCONV (see Figure 11).

fCLK = Clock frequency.

In the CONT, CMD and SYNS modes the conversion time, TCONV, is internally generated1. In the

SYND mode the conversion time is defined by the timing of the external pulses at the SYN pin and the

number of pulses stored in the EDGES register (see Figure 17 chapter 7.6 and chapter 8.2.7).

The number of clock counts within this interval is a constant number, which keeps the output result

independent of the internal clock frequency. In this case, the input light irradiance Ee, regarding the

area of the photodiode of the channel can be represented by Equation 2. In SYND mode Equation 3

represents the externally generated conversion time TCONV, and the conversion result. If the

conversion time measurement is activated

(CREG2:EN_TM = “1”) the number of clock counts within

the externally given conversion time can also be internally captured. So the input light irradiance Ee

regarding the photodiode’s area of the channel can be calculated as:

Equation 4:

MRES

OUTCONV

FSR





Where:

MRES = Digital output value of the conversion (content of output registers MRES1 to MRES3).

Ee =

Input light irradiance regarding the photodiode’s area within the conversion time interval.

FSREe = Full Scale Range of detectable input light irradiance Ee.

OUTCONV = Conversion time duration expressed as the number of clock counts within this time.

In this way, the input light irradiance can be measured independently of the internal frequency and the

external conversion time variations in SYND mode.

1 The system clock is internally generated and is subject to technological tolerances. As such, the clock frequency may vary,

which must be considered when calculating the time to be programmed (e.g. registers BREAK for pause time TBREAK or

CREG1:TIME for conversion time TCONV).

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