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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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PCAP01 Folha de dados(PDF) 66 Page - Sciosense B.V. |
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PCAP01 Folha de dados(HTML) 66 Page - Sciosense B.V. |
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66 / 96 page  PCapØ1Ax-0301 acam messelectronic gmbh - Friedrich-List-Str.4 - 76297 Stutensee - Germany - www.acam.de 5-15 Register 20 (address 20): 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Parameter Description Settings RUNBIT RUNBIT=1 must be the last parameter written. Please set RUNBIT=0 before making any modifications to the registry. 0 = protects the device and keeps it idle during configuration and forces the DSP to stand still. 1 = activates the run mode 5.2 Explanations to Configuration Registers 5.2.1 Comments on Register 0 Register 0 is the first in the list, and the last to be handled, as it applies to the OTP memory. So, during most of the evaluation and design-in, it will be unimportant. MEMCOMP: Setting 0x0 is mandatory if DSP_SRAM_SEL=‘OTP‘. Otherwise 0x2 may be best choice; upon firmware „stop“, the DSP clock will be slowed down, and SRA M contents will be compared to OTP in 33-byte parcels. Next parcel after next stop. Upon comparison alert, MEMCOMP issues a power-up reset. Through AUTOBOOT, the SRAM contents will be refreshed. ECC_MODE. When not disabled („single“), this mechanism stocks and compares OTP contents in redundancy, see OTP memory map in annex. Recommended setting is 0xF0 („quad“) for firmware length < 1985 bytes and 0x0F („double“) above. Quad mode simply means triple copy of every bit and AND connection between each (note: a ccidental zero-to- |
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