WM8593 datasheet(28/98 Pages) WOLFSON

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WM8593

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PP Rev 1.0 January 2007

DIGITAL AUDIO INTERFACE CONTROL

The control of the audio interface formats is achieved by register write. Dynamically changing the

audio data format may cause erroneous operation and is not recommended.

Interface timing is such that the input data and left/right clock are sampled on the rising edge of the

interface bit clock. Output data changes on the falling edge of the interface bit clock. By setting the

appropriate bit clock and left/right clock polarity bits, the WM8593 ADC and DACs can sample data

on the opposite clock edges.

The control of audio interface formats and clock polarities is summarised in Table 15.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

1:0

DAC1_

FMT[1:0]

DAC1 Audio Interface Format

00 = Right Justified

01 = Left Justified

10 = I

11 = DSP

3:2

DAC1_

WL[1:0]

DAC1 Audio Interface Word Length

00 = 16-bit

01 = 20-bit

10 = 24-bit

11 = 32-bit (not available in Right Justified

mode)

DAC1_BCP

DAC1 BCLK Polarity

0 = DACBCLK not inverted - data latched on

rising edge of BCLK

1 = DACBCLK inverted - data latched on

falling edge of BCLK

DAC1_CTRL1

02h

DAC1_LRP

DAC1 LRCLK Polarity

0 = DACLRCLK not inverted

1 = DACLRCLK inverted

1:0

DAC2_

FMT[1:0]

DAC2 Audio Interface Format

00 = Right Justified

01 = Left Justified

10 = I

11 = DSP

3:2

DAC2_

WL[1:0]

DAC2 Audio Interface Word Length

00 = 16-bit

01 = 20-bit

10 = 24-bit

11 = 32-bit (not available in Right Justified

mode)

DAC2_BCP

DAC2 BCLK Polarity

0 = DACBCLK not inverted - data latched on

rising edge of BCLK

1 = DACBCLK inverted - data latched on

falling edge of BCLK

DAC2_CTRL1

07h

DAC2_LRP

DAC2 LRCLK Polarity

0 = DACLRCLK not inverted

1 = DACLRCLK inverted

R13

ADC_CTRL1

0Dh

1:0

ADC_

FMT[1:0]

ADC Audio Interface Format

00 = Right Justified

01 = Left Justified

10 = I

11 = DSP

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