WM8593 datasheet(21/98 Pages) WOLFSON

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WM8593

PP Rev 1.0 January 2007

DEVICE ID AND REVISION

Reading from register R0 returns the device ID. Reading from register R1 returns the device revision

number.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DEVICE_ID

00h

15:0

DEVICE_ID

[15:0]

10000101

10010011

Device ID

A read of this register will return the device

ID, 0x8593.

REVISION

01h

7:0

REVNUM

[7:0]

N/A

Device Revision

A read of this register will return the device

revision number. This number is sequentially

incremented if the device design is updated.

Table 9 Device ID and Revision Number

GLOBAL ENABLE CONTROL

The WM8593 includes a number of enable and disable mechanisms to allow the device to be

powered on and off in a pop-free manner. A global enable control bit enables the ADC, DAC and

analogue paths.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R12

ENABLE

0Ch

GLOBAL_

Device Global Enable

0 = ADC, DAC and PGA ramp control

circuitry disabled

1 = ADC, DAC and PGA ramp control

circuitry enabled

Table 10 Global Enable Control

DIGITAL AUDIO INTERFACE

Digital audio data is transferred to and from the WM8593 via the digital audio interface. The DACs

have independent data inputs and master clocks, bit clocks and left/right frame clocks, and operate

in both master or slave mode The ADC has independent master clock, bit clock and left/right frame

clock in addition to its data output, and can operate in both master and slave modes.

MASTER MODE

The ADC audio interface requires both a left/right frame clock (ADCLRCLK) and a bit clock

(ADCBCLK). These can be supplied externally (slave mode) or they can be generated internally

(master mode). Selection of master and slave mode is achieved by setting ADC_MSTR in ADC

Control Register 3.

The frequency of ADCLRCLK in master mode is dependent upon the ADC master clock frequency

and the ADC_SR[2:0] bits.

The frequency of ADCBCLK in master mode can be selected by ADC_BCLKDIV[1:0].

The DAC audio interfaces require both left/right frame clocks (DACLRCLK1, DACLRCLK2) and bit

clocks (DACBCLK1, DACBCLK2). These can be supplied externally (slave mode) or they can be

generated internally (master mode). Selection of master and slave mode is achieved by setting

DAC1_MSTR in DAC1 Control Register 3 and DAC2_MSTR in DAC2 Control Register 3.

The frequency of DACLRCLK1 in master mode is dependent upon the DAC1 master clock frequency

and the DAC1_SR[2:0] bits. Similarly the frequency of DACLRCLK2 in master mode is dependent

upon the DAC2 master clock frequency and the DAC2_SR[2:0] bits.

The

frequency

DACBCLK1

and

DACBCLK2

master

mode

can

selected

DAC1_BCLKDIV[1:0] and DAC2_BCLKDIV[1:0].

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