WM8593 datasheet(86/98 Pages) WOLFSON

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WM8593

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PP Rev 1.0 January 2007

R41 (29h) – Audio Interface MUX Configuration Register 5 (AIF_MUX5)

Bit #

Read

Write

N/A

PORT5_UPD

DIO5_SEL[2:1]

Default

Bit #

Read

Write

DIO5_

SEL[0]

WORDCLK5_SEL[2:0]

MCLK5_SEL[2:0]

PORT5_

FORCE

Default

N/A = Not Applicable (no function implemented)

Function

Description

PORT5_FORCE

Force Port 5 Clocks to Change

0 = Wait until clocks are safe before switching between clock sources

1 = Force clock sources to change immediately

See Table 40 for details of use.

MCLK5_SEL[2:0]

MCLK5 Pin Function Select

000 = Output MCLK1

001 = Output MCLK2

010 = Output MCLK3

011 = Output MCLK4

100 = Input to WM8593

101 to 111 = Reserved

WORDCLK5_SEL[2:0]

BCLK5 and LRCLK5 Pins Function Select

000 = Output BCLK1 and LRCLK1

001 = Output BCLK2 and LRCLK2

010 = Output BCLK3 and LRCLK3

011 = Output BCLK4 and LRCLK4

100 = Inputs to WM8593

101 = Output DAC1BCLK and DAC1LRCLK (when DAC1 is in master mode)

110 = Output DAC2BCLK and DAC2LRCLK (when DAC2 is in master mode)

111 = Output ADCBCLK and ADCBCLK (when ADC is master mode)

DIO5_SEL[2:0]

DIO5 Pin Function Select

000 = Output DIO1

001 = Output DIO2

010 = Output DIO3

011 = Output DIO4

100 = Input to WM8593

101 = Output GPIO1

110 = Output GPIO2

111 = Output ADC Data Output

PORT5_UPD

Port 5 Update

0 = Latch corresponding Port 5 settings into Register Map but do not update

1 = Latch corresponding Port 5 settings into Register Map and update all simultaneously

Figure 57 R41 – Audio Interface MUX Configuration Register 5

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