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S32K310 Folha de dados(PDF) 24 Page - NXP Semiconductors

Nome de Peças S32K310
Descrição Electrónicos  Supports S32K344, S32K324, S32K314, S32K312, S32K311, S32K310, S32K341, S32K342 and S32K322. Data is preliminary for S32K328, S32K338, S32K348, S32K358 and S32K388
PDF  136 Pages
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Fabricante Electrônico  NXP [NXP Semiconductors]
Página de início  http://www.nxp.com
Logo NXP - NXP Semiconductors

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Table 9. HSE firmware memory verification time examples (continued)
Symbol
Description
Min
Typ
Max
Unit
Condition
Spec
Number
application firmware,
using AES-128
HMAC cipher.
D). CORE_CLK = 48
MHz; HSE_CLK = 48
MHz.
tRSA_64KB
Memory verification
of 64 KB of
application firmware,
using RSA 2048
cipher.
—
30.47
—
ms
Device running from
FIRC (clocking option
D). CORE_CLK = 48
MHz; HSE_CLK = 48
MHz.
—
tRSA_1024KB
Memory verification
of 1024 KB of
application firmware,
using RSA 2048
cipher.
—
51.6
—
ms
Device running from
FIRC (clocking option
D). CORE_CLK = 48
MHz; HSE_CLK = 48
MHz.
—
tECDSA_64KB
Memory verification
of 64 KB of
application firmware,
using ECDSA 521
bits cipher.
—
38.45
—
ms
Device running from
FIRC (clocking option
D). CORE_CLK = 48
MHz; HSE_CLK = 48
MHz.
—
tECDSA_1024KB
Memory verification
of 1024 KB of
application firmware,
using ECDSA 521
bits cipher.
—
59.56
—
ms
Device running from
FIRC (clocking option
D). CORE_CLK = 48
MHz; HSE_CLK = 48
MHz.
—
tSHA2_256_64KB
Memory verification
of 64 KB of
application firmware,
using SHA2 256 bits
bits cipher.
—
1.62
—
ms
Device running from
FIRC (clocking option
D). CORE_CLK = 48
MHz; HSE_CLK = 48
MHz.
—
tSHA2_256_
1024KB
Memory verification
of 1024 KB of
application firmware,
using SHA2 256 bits
bits cipher.
—
22.73
—
ms
Device running from
FIRC (clocking option
D). CORE_CLK = 48
MHz; HSE_CLK = 48
MHz.
—
tCMAC_64KB
Memory verification
of 64 KB of
application firmware,
using AES-128
CMAC cipher.
—
6.7
—
ms
Device running from
PLL (clocking option
A). CORE_CLK = 160
MHz; HSE_CLK = 80
MHz.
—
tCMAC_1024KB
Memory verification
of 1024 KB of
application firmware,
using AES-128
CMAC cipher.
—
104.8
—
ms
Device running from
PLL (clocking option
A). CORE_CLK = 160
MHz; HSE_CLK = 80
MHz.
—
Table continues on the next page...
NXP Semiconductors
Power management
S32K3xx Data Sheet, Rev. 8, 06/2023
Data Sheet: Technical Data
Preliminary Information for S32K3x8
24 / 136



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