S32K310 datasheet(21/136 Pages) NXP

21 / 136 page

For S32K388, applications running at 125°C Tamb, thermal management schemes at PCB level will have to be deployed to keep

TJ below 150°C.

5.4 ESD and Latch-up Protection Characteristics

Table 5. ESD and Latch-up Protection Characteristics

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

Vhbm

Electrostatic

discharge voltage,

human body model

(HBM) 1,2,3

-2000

—

2000

—

Vcdm

Electrostatic

discharge voltage,

charged-device

model (CDM),

all pins except

corner 1,3,4

-500

—

500

—

Vcdm

Electrostatic

discharge voltage,

charged-device

model (CDM), corner

pins 1,3,4

-750

—

750

—

Ilat

Latch-up current at

ambient temperature

of 125°C 5

-100

—

100

—

1. Device failure is defined as: "If after exposure to ESD pulses, the device does not meet specification requirements."

2. This parameter is tested in conformity with AEC-Q100-002.

3. All ESD testing conforms with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

4. This parameter is tested in conformity with AEC-Q100-011.

5. This parameter is tested in conformity with AEC-Q100-004.

6 Power management

6.1 Power mode transition operating behaviors

6.1.1 Power mode transition operating behavior

The values in the table below are provided for reference only.

Table 6. Power mode transition operating behavior

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

tMODE_

STDBYENTRY

RUN --> STANDBY

transition time

—

955

—

tMODE_

STDBYEXIT_FAST

STANDBY --> RUN

transition time, fast

standby exit

—

FIRC ON @48MHz in

Standby mode

—

Table continues on the next page...

NXP Semiconductors

Power management

S32K3xx Data Sheet, Rev. 8, 06/2023

Data Sheet: Technical Data

Preliminary Information for S32K3x8

21 / 136

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