REV. A

ADP3158/ADP3178

–10–

Note that there is a trade-off between converter efficiency and

cost. Larger MOSFETs reduce the conduction losses and allow

higher efficiency, but increase the system cost. If efficiency is not a

10 m

Ω nominal, 16 mΩ worst-case) for the high-side and a

Ω nominal,

10 m

Ω worst-case) for the low-side are good choices.

The high-side MOSFET dissipation is:

PI

R

VI

Q

f

I

PA

m

V

A

nC

kHz

A

W

DHSF

RMSHSF

DS ON

IN

L PEAK

G

MIN

G

DHSF

=×

+

××

×

×

=×

Ω +

××

×

×

=

2

2

2

88

16

5

15

70

195

21

175

()

()

..

(19)

where the second term represents the turn-off loss of the

provided by the ADP3159 is about 1 A.

The low-side MOSFET dissipation is:

PI

R

PA

m

W

DLSF

RMSLSF

DS ON

DLSF

=×

=×

Ω =

2

2

10 8

10

1 08

()

..

(20)

Note that there are no switching losses in the low-side MOSFET.

Surface mount MOSFETs are preferred in CPU core converter

applications due to their ability to be handled by automatic

assembly equipment. The TO-263 package offers the power

handling of a TO-220 in a surface-mount package. However,

this package still needs adequate copper area on the PCB to

help move the heat away from the package.

The junction temperature for a given area of 2-ounce copper

can be approximated using:

TP

T

AD

A

JJ

=×

θ

(21)

assuming:

θ

2

θ

2

θ

2

For 1 in

ambient temperature of 50

°C:

All of the above-calculated junction temperatures are safely

below the 175

°C maximum specified junction temperature of

the selected MOSFETs.

In continuous inductor-current mode, the source current of the

high-side MOSFET is approximately a square wave with a duty

maximum output current. To prevent large voltage transients, a

low ESR input capacitor sized for the maximum rms current

must be used. The maximum rms capacitor current is given by:

II

D

D

AA

C RMS

O

HSF

HSF

()

.

– ..

=−

=

=

2

2

15

0 36

0 36

7 2

(22)

For a ZA-type capacitor with 1000

µF capacitance and 6.3 V

voltage rating, the ESR is 24 m

Ω and the maximum allowable

ripple current at 100 kHz is 2 A. At 105

°C, at least four such

capacitors must be connected in parallel to handle the calculated

ripple current. At 50

°C ambient, however, a higher ripple cur-

rent can be tolerated, so three capacitors in parallel are adequate.

The ripple voltage across the three paralleled capacitors is:

VI

ESR

n

D

nC

f

VA

m

FkHz

mV

C IN RIPPLE

O

CIN

C

HSF

C

IN

MAX

C IN RIPPLE

()

()

()

%

=×

+

××









=×

Ω +

×µ ×









=

15

24

3

36

3 1000

195

129

(23)

To further reduce the effect of the ripple voltage on the system

supply voltage bus, and to reduce the input-current di/dt to

below the recommended maximum of 0.1 A/ms, an additional

small inductor (L > 1

µH @ 10 A) should be inserted between

the converter and the supply bus.

Feedback Compensation for Active Voltage Positioning

Optimized compensation of the ADP3158 and ADP3178 allows

the best possible containment of the peak-to-peak output voltage

deviation. Any practical switching power converter is inherently

limited by the inductor in its output current slew rate to a value

much less than the slew rate of the load. Therefore, any sudden

change of load current will initially flow through the output capaci-

tors, and this will produce an output voltage deviation equal to the

ESR of the output capacitor array times the load current change.

CH2

TEK RUN: 200kS/s SAMPLE

100mV

CH1

M 250 s

CH2

680mV

2

TRIG'D

Figure 4. Transient Response of the Circuit of Figure 3