DAC1653D datasheet(10/168 Pages) RENESAS

10 / 168 page

DAC1653D; DAC1658D

Datasheet

Rev. 2.41 — 28 April 2014

10 of 168

DAC1653D/DAC1658D

Dual 16-bit DAC: 10 Gbps JESD204B interface: x2, x4 and x8 interpolating

Datasheet

STATIC CHARACTERISTICS

9.1 Common characteristics

The DAC165xD requires supplies of both 3.3 V and 1.2 V or 1.3 V for DAC sample rate above 1.8 Gsps. The 1.2 V supply

has separate digital and analog power supply pins. The SPI power supply is flexible. It can be set from1.2 V to1.8 V (see

Section 11.2.1.1).

Table 5.

Common characteristics

VDDA(3V3) = 3.3 V; VDDA(1V2) = 1.2 V; VDDD(1V2) = 1.2 V; Typical values measured at Tamb = +25 C; IO(fs) = 20 mA; 1.5 Gsps sample rate

used; no auxiliary DAC used; no inverse sin(x)/x; no output correction; output signal = 1 Vpp,diff; unless otherwise specified.

Symbol

Parameter

Conditions

Test

[1]

Min

Typ

Max

Unit

Voltages

VDDA(3V3)

analog supply voltage

DAC1658D: high common

mode output

3.15

3.3

3.45

DAC1653D: low common

mode output

2.7[2]

3.3

3.45

VDDD(1V2)

digital supply voltage

1.14[3]

1.2

1.26

VDDA(1V2)

analog supply voltage

1.14

1.2

1.26

VDDD(IO)

I/O digital supply voltage

1.14

1.2

1.9

VDDD(sync)

digital supply voltage for

differential SYNC output

buffers

1.14

1.2

1.9

Clock inputs (pins CLKIN_P, CLKIN_N)

Vi(cm)

common-mode input

voltage. Internal

self-biased. AC-coupling

recommended

800

Vi(diff)

differential Peak-to-Peak

voltage

400

1000

2000

fin

Input frequency

compliance range

direct clocking

2000

MHz

harmonic clocking

(using clock divider)

3000

MHz

Ri(diff)

differential input resistor

100



input capacitance

Digital inputs/outputs (SYSREF_W_P/SYSREF_W_N, SYSREF_E_P/SYSREF_E_N)

Vi(cm)

common-mode input

voltage

VDDD(IO)=1.8V

800

1200

1400

VDDD(IO)=1.2V

800

950

1100

Vi(diff)

differential Peak-to-Peak

voltage

400

800

1000

Ri(diff)

differential input resistor

(could be disconnected see

Table 102)

100



input capacitance

0.7

Digital inputs (pins SDO, SDIO, SCLK, SCS_N, RESET_N)

VIL

LOW-level input voltage

GND

0.3VDDD(IO)

VIH

HIGH-level input voltage

0.7VDDD(IO)

-VDDD(IO)

DAC1653D Folha de dados(PDF) 10 Page - Renesas Technology Corp

DAC1653D Folha de dados(HTML) 10 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL