DAC1653D datasheet(52/168 Pages) RENESAS

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DAC1653D; DAC1658D

Datasheet

Rev. 2.41 — 28 April 2014

52 of 168

DAC1653D/DAC1658D

Dual 16-bit DAC: 10 Gbps JESD204B interface: x2, x4 and x8 interpolating

Datasheet

WCLK is the digital clock used for all logic related to the Digital Lane Processing (DLP) of the input interface. The divider

ratio WCLK_DIV_SEL (see Table 56) must be specified using the following equation:

(8)

Where:

• M stands for the number of DACs used inside the DAC165xD (M = 2)

Remark:

DAC165xD is a dual core device therefore M = 2. It is possible to use the device in a single core manner, but

the configuration must still be set to M = 2 and the related lanes and DAC core must be powered off.

• L stands for the number of serial input lanes used (L = 1, L = 2, or L = 4)

• INTERPOLATION stands for the interpolation factor specified in register INTERPOLATION (see Table 72).

Table 25 shows the results for nominal use cases

Clock divider and Group Delay configuration

To enable the Clock division, the dividers biasing should be powered on using PON_DCKDIV_1 and PON_DCKDIV_2 (see

Table 58). Then the division ratio CLKDIV_SEL_DIV needs to be configured and the default bypass mode must be disabled

(CLKDIV_CLK_BYP) see Table 60. In this mode, the CLKDIV_SEL_PHASE bits are used to specify the group delay

phase. The CLKDIV_SEL_DIV must be set during the DAC initialization phase only (see Table 60).

When changing the DAC clock phase during nominal usage, the DAC output will be kept at the previous value while the

new phase is set. For instance, setting the DAC clock phase from setting 0 to setting 1 will imply a 1.5 DAC clock constant

value. No glitches are expected during this phase.

Table 25.

WCLK_DIV selection

LMF configuration

Interpolation ratio

WCLK/DAC clock

WCLK_DIV_BYP

WCLK_DIV_SEL

421 / 422

1/4

010

1/8

100

1/16

110

222

1/2

000

1/4

010

1/8

100

124

xxx

1/2

000

1/4

010

211

1/2

000

1/4

010

1/8

100

Table 26.

CLKDIV_SEL_PHASE selection

CLKDIV_SEL_PHASE

000

DAC clock phase = 0

001

DAC clock phase = 1 x (CLK IN period ) /2

010

DAC clock phase = 2 x (CLK IN period) /2

011

DAC clock phase = 3 x (CLK IN period) /2

100

DAC clock phase = 4 x (CLK IN period) /2

WCLK

DAC _Clock

--------------------------------

INTERPOLATION





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