DAC1653D datasheet(86/168 Pages) RENESAS

86 / 168 page

DAC1653D; DAC1658D

Datasheet

Rev. 2.41 — 28 April 2014

86 of 168

DAC1653D/DAC1658D

Dual 16-bit DAC: 10 Gbps JESD204B interface: x2, x4 and x8 interpolating

Datasheet

11.9.1

JRES pin

The JRES pin is used for internal biasing of the RX PHY. The pin needs to be connected to a 6.98kOhms 1% resistor.

11.9.2

Lane input

Each lane is Current Mode Logic (CML) compliant.

The common-mode voltage and the termination resistor can be programmed using register HS_RX_RT_VCM (see

Table 162). When not used, the lane input buffer can be set to a high impedance mode (register HS_RX_RT_CTRL; see

Table 163).

AC-coupling is always required (see Figure 82).

Fig 81. RX PHY control overview

Vcm

Registers followed by a * can be read back at the same

position (address and bits) in block x0220 to check the

validation of the controlled action.

10.N

HS_RX_CDR_DIVN

HS_RX_CDR_DIVM

HS_RX_CDR_LOW_SPEED_EN

REFERENCES

HS_RX_RT_VCM_SEL*

HS_RX_RT_VCM_REF*

SYNC B

SYNC_SET_VCM

SYNC_SET_LVL

EQUALIZER

HS_RX_LN0_EQZ_IF_GAIN

HS_RX_LN0_RT_EN*

HS_RX_LN0_RT_HIZ_EN*

HS_RX_EQZ_AUTO_ZERO_EN

HS_RX_LN0_EQZ_EN*

AUTO_ZERO

VIN_P0

VIN_N0

BLOCK x0160: RX PHY / BLOCK x0180: RX PHY monitoring *

RESISTOR TERMINATION

HS_RX_LN0_RT_REF_SIZE

EQUALIZER

HS_RX_LN1_RT_EN* HS_RX_LN1_RT_HIZ_EN*

HS_RX_LN1_EQZ_EN*

VIN_P1

VIN_N1

RESISTOR TERMINATION

HS_RX_LN1_RT_REF_SIZE

HS_RX_LN2_RT_EN*

HS_RX_LN2_RT_HIZ_EN*

HS_RX_LN2 _EQZ_EN*

VIN_P2

VIN_N2

RESISTOR TERMINATION

HS_RX_LN2_RT_REF_SIZE

HS_RX_LN3_RT_EN*

HS_RX_LN3_RT_HIZ_EN*

SYNC_EN

HS_RX_LN3_EQZ_EN*

VIN_P3

VIN_N3

RESISTOR TERMINATION

HS_RX_LN3_RT_REF_SIZE

DCLK

(see block x0040)

EQUALIZER

HS_RX_LN1_EQZ_IF_GAIN

AUTO_ZERO

EQUALIZER

HS_RX_LN2_EQZ_IF_GAIN

AUTO_ZERO

EQUALIZER

HS_RX_LN3_EQZ_IF_GAIN

AUTO_ZERO

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