EM6607 datasheet(11/47 Pages) EMMICRO

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EM6607

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4.6

CPU State after RESET

RESET initialises the CPU as shown in the table below.

Table 7.

Initial Value after RESET

name

bits

symbol

initial value

Program counter 0

PC0

$000 (as a result of Jump 0)

Program counter 1

PC1

undefined

Program counter 2

PC2

undefined

stack pointer

SP(0) selected

index register

undefined

Carry flag

undefined

Zero flag

undefined

HALT

Instruction register

Jump 0

periphery registers

see peripheral memory map

4.7

POR with Power-Check Reset

POR and Power-Check are supervising the VREG (digital) which follows more or less the V

DD supply voltage on start-up

guarantee proper operation after Power-On. The resetcold signal is released when the V

DD supply voltage is high enough

for the IC to function correctly.

During power-up of the EM6607 static POR (Power-On-Reset) cell supervising the VREG with level of typ. 0.9V is checked to

give initial reset. Reset can be prolonged also with Power-Check function if enabled by metal option. In this case VDD must

come above VL1 of the SVLD described in Chapter

133H

134H

Supply Voltage Level Detector (SVLD) to release the circuit reset

signal and starts to execute instructions.

When Power-Check is enabled a power-check logic is switched-on with POR signal high and starts to check periodically

VDD against the SVLD-VL1 level which keeps resetcold active high until VDD > VL1. When used with external quartz first VDD

check starts in the middle of quartz Cold-Start sequence – after first 16384 system clocks with the same timing as in normal

SVLD operation. If VDD > VL1 Power-Check condition is met and system reset will wait until first 32768 clocks needed for

Quartz Cold-Start is finished and release System reset.

In case VDD < VL1, comparison will be repeated with every next 8 Hz system clock until VDD > VL1. In case of a very slow

rising VDD, it might happen that Quartz Cold-Start is finished. System reset will keep the EM6607 under reset until first time

VDD becomes higher as VL1 to guarantee good operating conditions (oscillator stabilized during its Cold-Start delay and VDD

is high enough to avoid “grey” zone between static POR and VL1).

IMPORTANT: special care should be taken, when Power Supply starts to fall close to or below V

DD min. Frequent checking

of the SVLD V

L1 (1.3V) must be done. Between minimum VDD supply of 1.2V and static POR level of 0.9V there is a grey

zone, which must be avoided for proper operation.

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