KSZ9567RTXI-TR datasheet(8/232 Pages) MICROCHIP

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KSZ9567R

DS00002329D-page 8

 2017-2019 Microchip Technology Inc.

2.0

INTRODUCTION

2.1

General Description

The KSZ9567R is a highly-integrated, IEEE 802.3 compliant networking device that incorporates a layer-2 managed

Gigabit Ethernet switch, five 10BASE-Te/100BASE-TX/1000BASE-T physical layer transceivers (PHYs) and associated

MAC units, and two MAC ports with individually configurable RGMII/MII/RMII interfaces for direct connection to a host

processor/controller, another Ethernet switch, or an Ethernet PHY transceiver.

The KSZ9567R is built upon industry-leading Ethernet technology, with features designed to offload host processing

and streamline the overall design:

• Non-blocking wire-speed Ethernet switch fabric supports 1 Gbps on RGMII

• Full-featured forwarding and filtering control, including port-based Access Control List (ACL) filtering

• Full VLAN and QoS support

• Traffic prioritization with per-port ingress/egress queues and by traffic classification

• Spanning Tree support

• IEEE 802.1X access control support

The KSZ9567R incorporates full hardware support for the IEEE 1588v2 Precision Time Protocol (PTP), including hard-

ware time-stamping at all PHY-MAC interfaces, and a high-resolution hardware “PTP clock”. IEEE 1588 provides sub-

microsecond synchronization for a range of industrial Ethernet applications.

The KSZ9567R fully supports the IEEE family of Audio Video Bridging (AVB) standards, which provides high Quality of

Service (QoS) for latency sensitive traffic streams over Ethernet. Time-stamping and time-keeping features support

IEEE 802.1AS time synchronization. All ports feature credit based traffic shapers for IEEE 802.1Qav, and a time aware

scheduler as proposed for IEEE 802.1Qbv.

A host processor can access all KSZ9567R registers for control over all PHY, MAC, and switch functions. Full register

access is available via the integrated SPI or I2C interfaces, and by in-band management via any one of the data ports.

PHY register access is provided by a MIIM interface. Flexible digital I/O voltage allows the MAC port to interface directly

with a 1.8/2.5/3.3V host processor/controller/FPGA.

Additionally, a robust assortment of power-management features including Wake-on-LAN (WoL) for low power standby

operation, have been designed to satisfy energy-efficient system requirements.

The KSZ9567R is available in an industrial (-40°C to +85°C) temperature range. An internal block diagram of the

KSZ9567R is shown in Figure 2-1.

FIGURE 2-1:

INTERNAL BLOCK DIAGRAM

KSZ9567R

Port 1

10/100/1000

PHY 1

10/100/1000

PHY 2

10/100/1000

PHY 3

10/100/1000

PHY 4

10/100/1000

PHY 5

Port 2

Port 3

Port 4

Port 5

GMAC 1

GMAC 2

GMAC 3

GMAC 4

GMAC 5

Control

Registers

GMAC 6

GMAC 7

RGMII/MII/RMII

Address

Lookup

MIB

Counters

Frame

Buffers

Queue

Mgmt.

SPI/I

2C/MIIM

IEEE 1588 /

802.1AS Clock

GPIO

Precision

GPIO

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