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S32K310 Folha de dados(PDF) 28 Page - NXP Semiconductors |
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S32K310 Folha de dados(HTML) 28 Page - NXP Semiconductors |
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28 / 137 page ![]() Table 8. Boot time, HSE firmware installed (continued) Symbol Description Min Typ Max Unit Condition Spec Number CORE_CLK @ 48 MHz (source = FIRC) tBOOT_HSE After a POR event, amount of time to execution of the first instruction of the application core, when HSE firmware is installed. Optional configuration: CORE_CLK @ 120 MHz (source = PLL) — 9.51 — ms — — tBOOT_HSE After a POR event, amount of time to execution of the first instruction of the application core, when HSE firmware is installed. Optional configuration: CORE_CLK @ 80 MHz (source = PLL) — 10.91 — ms — — 6.5.4 HSE firmware memory verification time examples Table 9. HSE firmware memory verification time examples Symbol Description Min Typ Max Unit Condition Spec Number tCMAC_64KB Memory verification of 64 KB of application firmware, using AES-128 CMAC cipher. — 11.3 — ms FIRC 48MHz — tCMAC_1024KB Memory verification of 1024 KB of application firmware, using AES-128 CMAC cipher. — 176 — ms FIRC 48MHz — tGMAC_64KB Memory verification of 64 KB of application firmware, using AES-128 GMAC cipher. — 3.2 — ms FIRC 48MHz — Table continues on the next page... NXP Semiconductors Power management S32K3xx Data Sheet, Rev. 5.2, 10/2022 Data Sheet: Technical Data Preliminary Information 28 / 137 |
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