RZSLASHT2M datasheet(18/127 Pages) RENESAS

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Table 1.17

Pin functions (5 of 7)

Classification

Pin name

I/O

Description

Serial communication

interface (SCI)

SCK0 to SCK5

I/O

Clock I/O pins (clock synchronous mode/simple SPI

mode/smart card mode)

RXD0 to RXD5

Input

Input the receive data (asynchronous mode/clock

synchronous mode/smart card mode)

TXD0 to TXD5

Output

Output the transmit data (asynchronous mode/clock

synchronous mode/smart card mode)

CTS0# to CTS5#

Input

Input the start of transmission (asynchronous mode/

clock synchronous mode) active-low

RTS0# to RTS5#

Output

Output the reception (asynchronous mode/clock

synchronous mode) active-low

SCL0 to SCL5

I/O

Input/output the I2C clocks (simple I2C mode)

SDA0 to SDA5

I/O

Input/output the I2C data (simple I2C mode)

MISO0 to MISO5

I/O

Input/output the data for slave transmission (simple SPI

mode)

MOSI0 to MOSI5

I/O

Input/output the data for master transmission (simple

SPI mode)

SS0# to SS5#

Input

Chip-select input pins (simple SPI mode) active-low

DE0 to DE5

Output

Driver enable output pins (asynchronous mode)

I2C bus interface (IIC)

IIC_SCL0 to IIC_SCL2

I/O

Clock I/O pins

IIC_SDA0 to IIC_SDA2

I/O

Data I/O pins

Ethernet

ETH0_TXCLK to ETH2_TXCLK

I/O

TX clock input pins (MII mode)

TX clock output pins (RGMII mode)

ETH0_TXD0 to ETH2_TXD0

Output

TX data 0 pins (RGMII, RMII, and MII modes)

ETH0_TXD1 to ETH2_TXD1

Output

TX data 1 pins (RGMII, RMII, and MII modes)

ETH0_TXD2 to ETH2_TXD2

Output

TX data 2 pins (RGMII and MII modes)

ETH0_TXD3 to ETH2_TXD3

Output

TX data 3 pins (RGMII and MII modes)

ETH0_TXEN to ETH2_TXEN

Output

TX data enable pins (RMII and MII modes)

TX data enable/TX data error (TX_CTL) pins (RGMII

mode)

ETH0_TXER to ETH2_TXER

Output

TX data error pins (MII mode)

ETH0_RXCLK to ETH2_RXCLK

Input

RX clock pins (RGMII, RMII, and MII modes)

ETH0_RXD0 to ETH2_RXD0

Input

RX data 0 pins (RGMII, RMII, and MII modes)

ETH0_RXD1 to ETH2_RXD1

Input

RX data 1 pins (RGMII, RMII, and MII modes)

ETH0_RXD2 to ETH2_RXD2

Input

RX data 2 pins (RGMII and MII modes)

ETH0_RXD3 to ETH2_RXD3

Input

RX data 3 pins (RGMII and MII modes)

ETH0_RXDV to ETH2_RXDV

Input

RX data valid pins (MII mode)

Carrier sense/RX data valid (CRS_DV) pins (RMII

mode)

RX data valid/RX error (RX_CTL) pins (RGMII mode)

ETH0_RXER to ETH2_RXER

Input

RX data error pins (RMII and MII modes)

ETH0_CRS to ETH2_CRS

Input

Carrier sense pins (MII mode)

ETH0_COL to ETH2_COL

Input

Collision detection pins (MII mode)

Ethernet MAC (GMAC)

GMAC_PTPTRG0

Input

PTP timer trigger external input 0

GMAC_PTPTRG1

Input

PTP timer trigger external input 1

GMAC_MDC

Output

Management data clock output pin

GMAC_MDIO

I/O

Management data I/O pin

RZ/T2M Datasheet

1. Overview

R01DS0383EJ0100 Rev.1.00

Mar 22, 2022

Page 18 of 127

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