RZSLASHT2M datasheet(4/127 Pages) RENESAS

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Table 1.5

I/O Ports

Feature

Functional description

General-purpose I/O ports

● 320-pin FBGA

– I/O pins: 193

– Input pins: 1

– Pull-up/pull-down resistors: 194

● 225-pin FBGA

– I/O pins: 134

– Input pins: 1

– Pull-up/pull-down resistors: 135

● 176-pin LQFP

– I/O pins: 118

– Input pins: 1

– Pull-up/pull-down resistors: 119

● 128-pin LQFP

– I/O pins: 70

– Input pins: 1

– Pull-up/pull-down resistors: 71

● The locations of input/output functions are selectable from among multiple pins.

Table 1.6

Event link

Feature

Functional description

Event Link Controller (ELC)

● Up to 213 event signals can be interlinked with the operation of modules.

● In particular, the operation of timer modules can be started by input event signals.

● Event-linked operation of signals of ports 16 and port 18 is to be possible.

Table 1.7

Timers (1 of 2)

Feature

Functional description

Multi-function timer pulse unit 3 (MTU3)

● 9 channels (16 bits × 8 channels, 32 bits × 1 channel)

● Maximum of 28 pulse-input/output and 3 pulse-input possible

● Select from among 10, 11, 12, or 14 counter-input clock signals for each channel (with

maximum operating frequency of 200 MHz)

● Input capture function

● 39 output compare/input capture registers

● Counter clear operation (synchronous clearing by compare match/input capture)

● Simultaneous writing to multiple timer counters (TCNT)

● Simultaneous register input/output by synchronous counter operation

● Buffered operation

● Support for cascade-connected operation

● Automatic transfer of register data

● Pulse output mode

Toggle/PWM/complementary PWM/reset-synchronized PWM

● Complementary PWM output mode

- Outputs non-overlapping waveforms for controlling 3-phase inverters

- Automatic specification of dead times

- PWM duty cycle: Selectable as any value from 0% to 100%

- Delay can be applied to requests for A/D conversion.

- Non-generation of interrupt requests at peak or trough values of counters can be selected.

- Double buffer configuration

● Reset synchronous PWM mode

Three phases of positive and negative PWM waveforms can be output with desired duty

cycles.

● Phase-counting mode: 16-bit mode (channels 1 and 2), 32-bit mode (channels 1 and 2 in

cascade connection)

● Counter functionality for dead-time compensation

● Generation of triggers for A/D converter conversion

● A/D converter start triggers can be skipped

● Digital noise filter function for signals on the input capture and external counter clock pins

● Event linking by the ELC

RZ/T2M Datasheet

1. Overview

R01DS0383EJ0100 Rev.1.00

Mar 22, 2022

Page 4 of 127

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