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RZ/T2M Folha de dados(PDF) 84 Page - Renesas Technology Corp |
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RZ/T2M Folha de dados(HTML) 84 Page - Renesas Technology Corp |
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84 / 127 page ![]() CKIO Tp Trc A25 to A0 tAD1 tCSD1 tRWD1 A12/A11*1 RD/WR# tCSD1 DACK*2 Tpw Trr tRWD1 D31 to D0 BS# tAD1 tAD1 CS3#, CS2# RAS# tRASD1 tRASD1 tCASD1 CAS# tCASD1 DQMUU, DQMUL, DQMLU, DQMLL (High) CKE Trc Trc tAD1 tRWD1 tCSD1 tCSD1 tRASD1 tRASD1 (Hi-Z) Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.33 Synchronous DRAM auto-refresh timing (WTRP = 1 cycle, WTRC = 3 cycles) RZ/T2M Datasheet 2. Electrical Characteristics R01DS0383EJ0100 Rev.1.00 Mar 22, 2022 Page 84 of 127 |
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