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RZ/T2M Folha de dados(PDF) 110 Page - Renesas Technology Corp

Nome de Peças RZ/T2M
Descrição Electrónicos  RZ Arm-based High-end 32 & 64-bit MPUs
PDF  127 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
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Table 2.39
Ethernet interface timing (MAC to MAC connection mode)
Parameter
Symbol
Min.
Max.
Unit
Reference
figure
Ethernet
(RGMII)
ETH2_TXCLK, ETH2_RXCLK cycle time
tMRGMIIck
7.2
8.8
ns
Figure 2.84
ETH2_TXCLK, ETH2_RXCLK frequency
Typ. 125 MHz
—
125 − 50 ppm
125 + 50 ppm
MHz
ETH2_TXCLK, ETH2_RXCLK duty clcle
—
45
55
%
ETH2_TXCLK, ETH2_TXD0 to ETH2_TXD3,
ETH2_TXEN (TX_CTL), ETH2_RXCLK,
ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV
(RX_CTL) rise/fall time
tMRGMIIr,
tMRGMIIf
—
0.75
ns
ETH2_TXD0 to ETHn_TXD3, ETHn_TXEN
(TX_CTL) output skew
tMRGMIIos
—
0.6
ns
ETH2_TXD0 to ETH2_TXD3, ETH2_TXEN
(TX_CTL) output setup time
tMRGMIIso
1.1
—
ns
ETH2_TXD0 to ETH2_TXD3, ETH2_TXEN
(TX_CTL) output hold time
tMRGMIIho
1.1
—
ns
ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV
(RX_CTL) input setup time
tMRGMIIsi
-0.7
—
ns
ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV
(RX_CTL) input hold time
tMRGMIIhi
2.9
—
ns
Ethernet
(MII)
ETH2_REFCLK cycle time
tMMIIck
40
—
ns
Figure 2.85
ETH2_REFCLK frequency Typ. 25 MHz
—
25 − 50 ppm
25 + 50 ppm
MHz
ETH2_TXD0 to ETH2_TXD3, ETH2_TXEN,
ETH2_TXER output delay time
tMMIId
11
25
ns
ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV,
ETH2_RXER setup time
tMMIIs
10
—
ns
ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV,
ETH2_RXER hold time
tMMIIh
0
—
ns
RZ/T2M Datasheet
2. Electrical Characteristics
R01DS0383EJ0100 Rev.1.00
Mar 22, 2022
Page 110 of 127



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