R5F5671CDDFM datasheet(2/178 Pages) RENESAS

2 / 178 page

RX671 Group

1. Overview

R01DS0373EJ0110 Rev.1.10

Page 2 of 178

Apr 15, 2022

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different

packages.

Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the

modules differ depending on the number of pins on the package. For details, see Table 1.2, Comparison of Functions

for Different Packages.

Table 1.1

Outline of Specifications (1/10)

Classification

Module/Function

Description

CPU

• Maximum operating frequency: 120 MHz

• 32-bit RX CPU (RXv3)

• Minimum instruction execution time: One instruction per state (cycle of the system

clock)

• Address space: 4-Gbyte linear

• Register set of the CPU

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

• 113 instructions

Instructions installed as standard: 111

Basic instructions: 77

Single-precision floating-point operation instructions: 11

DSP instructions: 23

Instructions for register bank save function: 2

• Addressing modes: 11

• Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

• On-chip 32-bit multiplier: 32 × 32 → 64 bits

• On-chip divider: 32 / 32 → 32 bits

• Barrel shifter: 32 bits

FPU

• Single precision (32-bit) floating point

• Data types and floating-point exceptions in conformance with the IEEE754 standard

Double-precision

floating point

coprocessor

• Double-precision floating-point register set

Double-precision floating-point data registers: 16, each with 64-bit width

Double-precision floating-point control registers: Four, each with 32-bit width

• Double-precision floating-point processing instructions: 21

• Notifying the interrupt controller of double-precision floating-point exceptions

function

• Fast collective saving and restoration of the values of CPU registers

• 16 save register banks

Memory

Code flash memory

• Capacity: 1 Mbyte/1.5 Mbytes/2 Mbytes

• ROM cache: 8 Kbytes

• 60 MHz ≤ No-wait cycle access

120 MHz

≤ 1-wait cycle access

• Instructions hitting the ROM cache or operand = 120 MHz: No-wait access

• On-board programming: Four types

• Off-board programming (parallel programmer mode)

• Instructions are executable only for the program stored in the TM target area by using

the Trusted Memory (TM) function and protection against data reading is realized.

• A dual-bank structure allows programming during reading or exchanging the start-up

areas

Data flash memory

• Capacity: 8 Kbytes

• Programming/erasing: 100,000 times

Unique ID

• 16-byte unique ID for the device

RAM

• Capacity: 384 Kbytes

• 120 MHz, no-wait access

Standby RAM

• Capacity: 4 Kbytes

• Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access

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