R5F5671CDDFM datasheet(1/178 Pages) RENESAS

Nome de Peças	R5F5671CDDFM

Descrição Electrónicos	120-MHz 32-bit RX MCU, on-chip double-precision FPU, 707 CoreMark, up to 2-MB flash memory (supporting the dual bank function), 384-KB SRAM, various communications interfaces, including SD host interface, Quad SPI, and CAN, Capacitive touch sensing unit,

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

Página de início	http://www.renesas.com

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RX671 Group

Renesas MCUs

Datasheet

R01DS0373EJ0110 Rev.1.10

Page 1 of 178

Apr 15, 2022

Features

■ 32-bit RXv3 CPU core

• Maximum operating frequency: 120 MHz

Capable of 707 CoreMark in operation at 120 MHz

• Double-precision 64-bit IEEE-754 floating point

• A collective register bank save function is available.

• Supports the memory protection unit (MPU)

• JTAG and FINE (one-line) debugging interfaces

■ Low-power design and architecture

• Operation from a single 2.7- to 3.6-V supply

• Battery supply of backup power allows continued operations of the

RTC and the backup registers.

• Four low-power modes

■ On-chip code flash memory

• Supports versions with up to 2 Mbytes of ROM

• No wait cycles at up to 60 MHz or when the ROM cache is hit, one-

wait state at up to 120 MHz

• User code is programmable by on-board or off-board programming.

• Programming/erasing as background operations (BGOs)

• A dual-bank structure allows exchanging the start-up bank.

■ On-chip data flash memory

• 8 Kbytes, reprogrammable up to 100,000 times

• Programming/erasing as background operations (BGOs)

■ On-chip SRAM

• 384 Kbytes of SRAM (no wait states)

• 4 Kbytes of standby RAM (backup on deep software standby)

■ External address space

• Buses for full-speed data transfer (maximum operating frequency of

60 MHz)

• 8 CS areas

• 8- or 16-bit bus space is selectable per area

• Independent SDRAM area (128 Mbytes)

■ Data transfer

• DMACAb: 8 channels

• DTCb: 1 channel

• EXDMACa: 2 channels

■ Reset and supply management

• Power-on reset (POR)

• Low voltage detection (LVD) with voltage settings

• Backup domain low power detection

■ Clock functions

• External crystal resonator or internal PLL for operation at 8 to 24

MHz

• A sub-clock oscillator connectable to a 32.768-kHz crystal resonator

• Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20

MHz

• 120-kHz clock for the IWDTa

■ Real-time clock

• Adjustment functions (30 seconds, leap year, and error)

• Real-time clock counting and binary counting modes are selectable

• Time capture in response to an event-signal input

■ Independent watchdog timer

• Operates with the 120-kHz clock frequency generated by the

dedicated low-speed oscillator

■ Useful functions for IEC60730 compliance

• Oscillation-stoppage detection, frequency measurement, CRCA,

IWDTa, self-diagnostic function for the A/D converter, etc.

• Register write protection function that protects important registers

against overwriting

■ Remote control signal receiver

■ Various communications interfaces

• PHY layer (up to 2 channels) for host/function or OTG controller

(1 channel) with full-speed USB 2.0 transfer

• CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up

to 2 channels)

• SCIk and SCIh with multiple functionalities (up to 13 channels)

Choose from among asynchronous mode, clock-synchronous mode,

smart-card interface mode, simplified SPI, simplified I2C, and

extended serial mode.

• SCIm with 16-byte transmission and reception FIFOs (up to 2

channels)

• Up to two RSCIs with Manchester encoding and HBS functionality

• The I2C bus interfaces RIIC and RIICHS for transfer at up to 3.4

Mbps (up to 3 channels), and the RIICHS also supports high-speed

mode.

• Single I/O RSPId (3 channels), single I/O RSPIA (1 channel), and

quad QSPIX (1 channel). The QSPIX supports fetching from serial

flash memory.

• SD host interface (1 channel) with a 1- or 4-bit SD bus for use with

SD memory or SDIO

• Serial sound interface supporting various audio data formats,

including I2S

■ Up to 25 extended-function timers

• 16-bit TPUa, MTU3a

• 8-bit TMRb (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2

channels)

■ 12-bit A/D converter

• Two 12-bit units (8 channels for unit 0; 12 channels for unit 1)

• Self diagnosis, detection of analog input disconnection

■ Temperature sensor for measuring temperature

within the chip

■ Capacitive touch sensing unit

• Self-capacitance method: A single pin configures a single key,

supporting up to 17 keys

• Mutual capacitance method: Matrix configuration with 17 pins,

supporting up to 64 keys

■ Encryption function

• Trusted Secure IP (TSIP)

AES128/192/256, TDES, ARC4, RSA, ECC,

True-random number generator (TRNG), SHA1, SHA224, SHA256,

MD5, GHASH, Prevention of the illicit copying of keys

■ Up to 114 pins for general I/O ports

• 5-V tolerance, open drain, input pull-up, switchable driving ability

■ Operating temp. range

• D-version: –40°C to +85°C

• G-version: –40°C to +105°C

PLQP0144KA-B 20 × 20 mm, 0.50-mm pitch

PLQP0100KB-B 14 × 14 mm, 0.50-mm pitch

PLQP0064KB-C 10 × 10 mm, 0.50-mm pitch

PTLG0145JC-A 9 × 9 mm, 0.65-mm pitch

PTLG0145KB-A 7 × 7 mm, 0.50-mm pitch

PTLG0100JB-A 7 × 7 mm, 0.65-mm pitch

PTBG0064KB-A 4.5 × 4.5 mm, 0.50-mm pitch

PWQN0048KC-A 7 × 7 mm, 0.50-mm pitch

120-MHz 32-bit RX MCU, on-chip double-precision FPU, 707 CoreMark,

up to 2-MB flash memory (supporting the dual bank function), 384-KB SRAM,

various communications interfaces, including SD host interface, Quad SPI, and CAN, Capacitive touch sensing unit,

12-bit A/D converter, RTC, Encryption function, Serial sound interface, Remote control signal receiver

R01DS0373EJ0110

Rev.1.10

Apr 15, 2022

Features

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