R5F5671CDDFM datasheet(7/178 Pages) RENESAS

Nome de Peças	R5F5671CDDFM

Descrição Electrónicos	120-MHz 32-bit RX MCU, on-chip double-precision FPU, 707 CoreMark, up to 2-MB flash memory (supporting the dual bank function), 384-KB SRAM, various communications interfaces, including SD host interface, Quad SPI, and CAN, Capacitive touch sensing unit,

PDF	178 Pages

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

Página de início	http://www.renesas.com

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7 / 178 page

RX671 Group

1. Overview

R01DS0373EJ0110 Rev.1.10

Page 7 of 178

Apr 15, 2022

Timers

Programmable pulse

generator (PPG)

• (4 bits × 4 groups) × 2 units

• Pulse output with the MTU or TPU output as a trigger

• Maximum of 32 pulse-output possible

Realtime clock (RTCd)*1

• Clock sources: Main clock, sub clock

• Selection of the 32-bit binary count in time count/second unit possible

• Clock and calendar functions

• Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt

• Battery backup operation

• Time capture function (up to 3 pins)

• Event linking by the ELC

Communication

function

USB 2.0 FS host/

function module (USBb)

• Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS

• Up to two ports

• Compliance with the USB 2.0 specification

• Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only)

• Both self-powered mode and bus-powered mode are supported

• OTG (On the Go) operation is possible (low-speed is not supported)

• Incorporates 2 Kbytes of RAM as a transfer buffer

• External pull-up and pull-down resistors are not required

Serial communications

interfaces

(SCIk, SCIm, SCIh)

• 13 channels (SCIk: 10 channels + SCIh: 1 channel + SCIm: 2 channels)

• SCIk, SCIh, SCIm

Serial communications modes: Asynchronous, clock synchronous, and smart-card

interface

Multi-processor function

On-chip baud rate generator allows selection of the desired bit rate

Choice of LSB-first or MSB-first transfer

Start-bit detection: Level or edge detection is selectable.

Simple I2C

Simple SPI

9-bit transfer mode

Bit rate modulation

Double-speed mode

• SCIk, SCIh

Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12

Event linking by the ELC (only on channel 5)

• SCIh

Supports the serial communications protocol, which contains the start frame and

information frame

Supports the LIN format

• SCIm

Data can be transmitted or received in sequence by the 16-byte FIFO buffers of the

transmission and reception unit

• SCIk, SCIm

Data match detection

Adjustment of the timing of sampling of the RXD signals

Table 1.1

Outline of Specifications (6/10)

Classification

Module/Function

Description

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