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AS3956 Folha de dados(PDF) 31 Page - ams AG |
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AS3956 Folha de dados(HTML) 31 Page - ams AG |
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31 / 107 page ![]() ams Datasheet Page 31 [v1-11] 2018-Nov-14 Document Feedback AS3956 − Detailed Description Fabrication Data FAB_CFG1 Figure 28: Fabrication Data FAB_CFG1 Note(s): 1. This byte can be set only during production. The fdel bits define frame delay time (FDT) adjustment and represent a time compensation in number of clocks of carrier frequency. The osct bits are trimming bits for the internal oscillator. Fabrication Data FAB_CFG2 Figure 29: Fabrication Data FAB_CFG2 Note(s): 1. This byte can be set only during the production in a chip test mode. Conf. Bit Name Default Function Note b7 fdel<3> 0 PCD to PICC frame delay time compensation; frame compensation defined as fdel*1/fc b6 fdel<2> 0 b5 fdel<1> 0 b4 fdel<0> 0 b3 osct<1> 0 Oscillator trimming bits b2 osct<0> 0 b1 decc<1> 0 Decoder compensation register b0 decc<0> 0 Conf. Bit Name Default Function Note b7 test_mode 0 0: Test mode is disabled b6 mod_r 0 1: The modulator switch resistance is decreased b5 i2c_pu 0 1: Enable pull-ups for SDA and SCL when I²C is used b4 miso_pd1 0 1: Pull down on MISO when \SS is high b3 NA 0 Do not change from default b2 rfu 0 Reserved for future use b1 rfu 0 Reserved for future use b0 rfu 0 Reserved for future use |
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