ADP1048WARQZ-R7 datasheet(70/82 Pages) AD

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ADP1048W

Data Sheet

CURRENT LOOP FILTER GAIN FOR LOW LINE INPUT REGISTER

Table 102. Register 0xFE29—Current Loop Filter Gain for Low Line Input

Bits

Bit Name

R/W

Description

[7:0]

Current loop filter

gain for low line

R/W

These bits set the current loop digital filter gain of the PFC current loop under the low line input

voltage.

CURRENT LOOP FILTER ZERO FOR LOW LINE INPUT REGISTER

Table 103. Register 0xFE2A—Current Loop Filter Zero for Low Line Input

Bits

Bit Name

R/W

Description

[7:0]

Current loop filter

zero for low line

R/W

These bits set the current loop digital filter zero of the PFC current loop under the low line input

voltage.

CURRENT LOOP FILTER GAIN FOR HIGH LINE INPUT REGISTER

Table 104. Register 0xFE2B—Current Loop Filter Gain for High Line Input

Bits

Bit Name

R/W

Description

[7:0]

Current loop filter

gain for high line

R/W

These bits set the current loop digital filter gain of the PFC current loop under the high line

input voltage.

CURRENT LOOP FILTER ZERO FOR HIGH LINE INPUT REGISTER

Table 105. Register 0xFE2C—Current Loop Filter Zero for High Line Input

Bits

Bit Name

R/W

Description

[7:0]

Current loop filter

zero for high line

R/W

These bits set the current loop digital filter zero of the PFC current loop under the high line

input voltage.

SOFT START SET REGISTER

Table 106. Register 0xFE2D—Soft Start Set

Bits

Bit Name

R/W

Description

[7:6]

RSVD

Reserved.

[5:3]

Soft start delay time

R/W

These bits set the delay time between the inrush signal and the beginning of the soft start.

Bit 5

Bit 4

Bit 3

Number of Full AC Line Cycles

[2:0]

Soft start time

R/W

These bits set the soft start time.

Bit 2

Bit 1

Bit 0

Time

112 ms

168 ms

224 ms

280 ms

392 ms

504 ms

616 ms

728 ms

Rev. 0 | Page 70 of 82

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