SST26VF040A-80ISLASHMFVXX datasheet(5/73 Pages) MICROCHIP

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DS20006292B-page 5

SST26VF040A

3.0

MEMORY ORGANIZATION

The SST26VF040A SQI memory array is organized in

uniform, 4-Kbyte erasable sectors with the following

erasable blocks: with 32-Kbyte overlay erasable blocks

and 64-Kbyte overlay erasable blocks.

4.0

DEVICE OPERATION

SST26VF040A supports both

Serial Peripheral

Interface (SPI) bus protocol and a 4-bit multiplexed SQI

bus protocol. To provide backward compatibility to

traditional SPI Serial Flash devices, the device’s initial

state after a Power-on Reset is SPI mode which

supports multi-I/O (x1/x2/x4) read/write commands. A

command instruction configures the device to SQI

mode. The dataflow in the SQI mode is similar to the

SPI mode, except it uses four multiplexed I/O signals

for command, address, and data sequence.

SQI Flash memory supports both Mode 0 (0,0) and

Mode 3 (1,1) bus operations. The difference between

the two modes is the state of the SCK signal when the

bus host is in Standby mode and no data is being trans-

ferred. The SCK signal is low for Mode 0 and SCK sig-

nal is high for Mode 3. For both modes, the Serial Data

I/O (SIO[3:0]) is sampled at the rising edge of the SCK

clock signal for input, and driven after the falling edge

of the SCK clock signal for output. The traditional SPI

protocol uses separate input (SI) and output (SO) data

signals as shown in Figure 4-1. The SQI protocol uses

four multiplexed signals, SIO[3:0], for both data in and

data out, as shown in Figure 4-2. This means the SQI

protocol quadruples the traditional bus transfer speed

at the same clock frequency, without the need for more

pins on the package.

FIGURE 4-1:

SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)

FIGURE 4-2:

SQI SERIAL QUAD I/O PROTOCOL

MODE 3

SCK

CE#

MODE 3

Don’t Care

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

High-Impedance

MSB

MODE 3

CLK

SIO[3:0]

CE#

MODE 3

MODE 0

MSB

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