SST26VF040A-80ISLASHMFVXX datasheet(19/73 Pages) MICROCHIP

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DS20006292B-page 19

SST26VF040A

FIGURE 5-7:

HIGH-SPEED READ SEQUENCE (SQI)

5.7

SPI Quad Output Read

The SPI Quad Output Read instruction supports fre-

quencies of up to 104 MHz from 2.7V-3.6V and up to

80 MHz from 2.3V-3.6V. SST26VF040A requires the

IOC bit in the Configuration register to be set to ‘1’ prior

to executing the command. Initiate SPI Quad Output

Read by executing an 8-bit command, 6BH, followed

by address bits A[23:0] and a dummy byte. CE# must

remain active-low for the duration of the SPI Quad

Mode Read. See Figure 5-8 for the SPI Quad Output

Read sequence.

Following the dummy byte, the device outputs data

from SIO[3:0] starting from the specified address

location. The device continually streams data output

through all addresses until terminated by a low-to-high

transition on CE#. The internal Address Pointer

automatically increments until the highest memory

address is reached, at which point the Address Pointer

returns to the beginning of the address space.

FIGURE 5-8:

SPI QUAD OUTPUT READ

Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble

Hx = High Data Nibble, Lx = Low Data Nibble C[1:0] = 0BH

Address

Dummy

Command

Data Byte 0

MSN

LSN

Data Byte 7

Mode

SCK

SIO[3:0]

CE#

XH0

MODE 3

MODE 0

913

M1 M0

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble

CE#

SIO0

SCK

012345678

31 32

MODE 3

MODE 0

15 16

6BH

39 40 41

A[23:16] A[15:8]

A[7:0]

b4 b0

b5 b1

b6 b2

b7 b3

SIO1

SIO2

SIO3

Address

OP Code

Data

Byte 0

Dummy

Data

Byte N

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