SST26VF040A-80ISLASHMFVXX datasheet(31/73 Pages) MICROCHIP

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DS20006292B-page 31

SST26VF040A

5.21

SPI Quad Page Program

The SPI Quad Page Program instruction programs up

to 256 bytes of data in the memory. The data for the

selected page address must be in the erased state

(FFH) before initiating the SPI Quad Page Program

operation. A SPI Quad Page Program applied to a

protected memory area will be ignored. SST26VF040A

requires the ICO bit in the Configuration register to be

set to ‘1’ prior to executing the command. Prior to the

program operation, execute the WREN instruction.

To execute a SPI Quad Page Program operation, the

host drives CE# low then sends the SPI Quad Page

Program command cycle (32H), three address cycles

followed by the data to be programmed, then drives

CE# high. The programmed data must be between 1 to

256 bytes and in whole-byte increments. The com-

mand cycle is eight clocks long, the address and data

cycles are each two clocks long, Most Significant bit

first. Poll the BUSY bit in the STATUS register, or wait

TPP for the completion of the internal, self-timed, write

operation. See Figure 5-29.

When executing SPI Quad Page Program, the memory

range for the SST26VF040A is divided into 256-byte

page boundaries. The device handles shifting of more

than 256 bytes of data by maintaining the last

256 bytes of data as the correct data to be

programmed. If the target address for the SPI Quad

Page Program instruction is not the beginning of the

page boundary (A[7:0] are not all zero), and the of

bytes of data input exceeds or overlaps the end of the

address of the page boundary, the excess data inputs

wrap-around and will be programmed at the start of that

target page.

FIGURE 5-29:

SPI QUAD PAGE-PROGRAM SEQUENCE

5.22

Write Suspend and Write Resume

Write Suspend allows the interruption of Sector Erase,

32-Kbyte Block Erase, 64-Kbyte Block Erase, SPI

Quad Page Program, or Page Program operations in

order to erase, program or read data in another portion

of memory. The original operation can be continued

with the Write Resume command. This operation is

supported in both SQI and SPI protocols.

Only one write operation can be suspended at a time;

if an operation is already suspended, the device will

ignore the Write Suspend command. Write Suspend

during Chip Erase is ignored; Chip Erase is not a valid

command while a write is suspended.

The Write Resume command is ignored until any write

operation (Program or Erase) initiated during the Write

Suspend is complete. The device requires a minimum

of 500 µs between each Write Suspend command.

A20A16A12 A8 A4 A0 b4 b0

CE#

SIO0

SCK

012345678

16 17

MODE 3

MODE 0

910 11

32H

SIO1

SIO2

SIO3

Address

Data

Byte 1

13 14

A21 A17A13 A9 A5 A1 b5 b1 b5 b1

b5 b1

A22 A18A14A10 A6 A2 b6 b2 b6 b2

b6 b2

A23 A19 A15 A11 A7 A3 b7 b3 b7 b3

b7 b3

Data

Byte 0

Data

Byte

255

MSN LSN

b4 b0

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