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FXLS8967AF Folha de dados(PDF) 79 Page - NXP Semiconductors

Nome de Peças FXLS8967AF
Descrição Electrónicos  3-Axis Low-g Accelerometer
PDF  98 Pages
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Fabricante Electrônico  NXP [NXP Semiconductors]
Página de início  http://www.nxp.com
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FXLS8967AF Folha de dados(HTML) 79 Page - NXP Semiconductors

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NXP Semiconductors
FXLS8967AF
3-Axis Low-g Accelerometer
Field
Description
3 to 0
ST_DEC
Self-Test measurement phase decimation factor
This bit field selects the Self-Test measurement phase decimation factor.
The decimation selection ranges from 1 to 4096 as shown in Table 120.
Table 119. SELF_TEST_CONFIG2 register (address 38h) bit description
ST_DEC[3] ST_DEC[2] ST_DEC[1] ST_DEC[0] Decimation
selection
(Number of
samples
Self-Test
measurement
period
(ms)
Self-Test ODR
(Hz)
0
0
0
0
1
0.3125
3200
0
0
0
1
2
0.625
1600
0
0
1
0
4
1.25
800
0
0
1
1
8
2.5
400
0
1
0
0
16
5
200
0
1
0
1
32
10
100
0
1
1
0
64
20
50
0
1
1
1
128
40
25
1
0
0
0
256
80
12.5
1
0
0
1
512
160
6.25
1
0
1
0
1024
320
3.125
1
0
1
1
2048
640
1.563
1
1
0
0
4096
1280
0.78125
1
1
0
1
4096
1280
0.78
1
1
1
0
4096
1280
0.781
1
1
1
1
4096
1280
0.781
Table 120. Self-Test measurement phase decimation settings
Notes:
• During the self-test sequence, the accelerometer measurement period in μs (for each
axis and each direction) is given by Equation 4.
(4)
• The user-selected ODR and power mode settings are ignored during self-test
operation. The user-selected settings for ODR and power mode are applied after self-
test is disengaged, for example,
SENSCONFIG1[...]ST_AXIS_SEL[1:0] = 00b.
FXLS8967AF
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Objective data sheet
Rev. 1 — 27 April 2021
79 / 98



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