FXLS8967AF datasheet(75/98 Pages) NXP

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NXP Semiconductors

FXLS8967AF

3-Axis Low-g Accelerometer

aaa-040849

N+1

N-1

Previous reference

SDCD compare using previous reference and decimator data N

Reference is updated after comparison with decimator data N

SDCD compare using updated reference and decimator data N = 1

ADC sample

Decimator output

Decimator ODR

l2C write ref_upd

ref_upd

Updated reference with decimator data N

Figure 18. SDCD REF_UPD timing diagram

15.31.5 SDCD_OT_DBCNT register (address 31h)

Debounce count threshold register for SDCD outside-of-thresholds condition event

detection.

The timer count period is equal to the selected ODR period in LPM and HPM modes, and

to the effective ODR period (measurement + idle time) in FPM.

This register sets the minimum number of debounce counts needed to recognize the

SDCD outside-of-threshold function event condition as true.

A transition from Standby to Active, Active to Standby, or Auto-WAKE/SLEEP mode

change resets the internal counter.

Bit

Name

SDCD_OT_DBCNT[7:0]

Reset (BT_MODE = GND)

Reset (BT_MODE = VDD)

Access

R/W

Table 104. SDCD_OT_DBCNT register (address 31h) bit allocation

Field

Description

7 to 0

SDCD_OT_

DBCNT[7:0]

This value defines the minimum number of debounce counts required for the detection of an outside-

of-thresholds condition. The OT_DBCNTM bit determines the behavior of the counter when the

condition of interest is false. The time step for the counter is the same as the selected ODR period (or

effective ODR period in FPM).

Table 105. SDCD_OT_DBCNT register (address 31h) bit description

15.31.6 SDCD_WT_DBCNT register (address 32h)

Debounce count threshold register for SDCD within-thresholds condition event detection.

The timer count period is equal to the selected ODR period in LPM and HPM modes, and

to the effective ODR period (measurement + idle time) in FPM.

FXLS8967AF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

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