FXLS8967AF datasheet(39/98 Pages) NXP

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NXP Semiconductors

FXLS8967AF

3-Axis Low-g Accelerometer

15.7 BUF_X_LSB, BUF_X_MSB, BUF_Y_LSB, BUF_Y_MSB, BUF_Z_LSB,

BUF_Z_MSB (addresses 0Ch to 11h)

These registers contain either the buffer Head or Tail output acceleration sample data in

2's complement format. The tail (oldest) sample is stored when the FIFO read out mode

is selected, and the head (newest) sample is stored when the LIFO read out mode is

selected.

BUF_CONFIG1[BUF_TYPE] controls the read out mode.

The byte order of the output data is programmable via

SENS_CONFIG2[LE_BE], and

defaults to little-endian mode.

In little-endian mode, the output data buffer registers are arranged with the LSB of each

axes data stored at the lower address. The upper nibble (MSB) is stored at the next

address, and is right justified. In little-endian mode, the buffer output data is also sign

extended to avoid the need for the host software to do sign extension of the output data

on a per sample (per axis) basis.

In big-endian mode (with

SENS_CONFIG2[LE_BE] = 1), the output buffer data registers

are arranged with the MSB of each axis data stored at the lower register address. The

lower nibble(LSB) is stored at the next address, and is left justified. The lower 4 bits of

the LSB are always read as '0'. The host software must right shift the data by 4 bits (or

divide the value by 16) in order to obtain the correct scaling of the acceleration data.

SENS_CONFIG2[F_READ] = 1, the auto increment mechanism skips over the MSB

registers. This operation shortens the output data size from 6 bytes to 3 bytes per

XYZ sample. When

SENS_CONFIG2[F_READ] = 1, the MSB of each axes data is

stored at the LSB address, regardless of the setting made in

SENS_CONFIG2[LE_BE].

The output data size may also be reduced using the X/Y/Z_DIS bits located in the

SENS_CONFIG5 register. These bits can be used to selectively disable each axis from

being read out using the auto-increment mechanism. For example, setting X_DIS causes

the auto-increment mechanism to skip over the

BUF_X LSB and MSB registers, thereby

shortening the number of bytes to be read from 6 to 4, or from 3 to 2 when F_READ = 1.

Note: Reading the BUF_STATUS register is not required in order to clear the

BUF_WMRK event flag - if the host has mapped more than the BUF_WMRK event flag

to the same interrupt pin, the

BUF_STATUS register should be used to confirm that

a BUF_WMRK event was the source of the interrupt before initiating the burst read

operation.

Bit

Name

BUF_X[7:0]

Reset

—

Access

Table 36. BUF_X_LSB and BUF_X_MSB registers (addresses 0Ch, 0Dh) with SENS_CONFIG2[LE_BE] = 0 bit

allocation

Bit

Name

BUF_X[11:8]

Reset

—

Access

FXLS8967AF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

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