VSC880TY datasheet(3/28 Pages) VITESSE

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC880

High Performance 16x16

Serial Crosspoint Switch

G52191-0, Rev 4.2

Page 3

01/05/01

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

RESYNEN

Resynch Enable

<1MHz

TTL

If RESYNEN is HIGH, all links that have a link error

condition will be reinitialized. This will override the internal

control register settings.

INT

Interrupt

<1MHz

TTL

If INT is LOW, a receive error has occurred in one of the

links that has it’s output enable (OE) bit set HIGH and

interrupt control register bit set HIGH.

MEN

Reserved

<1MHz

TTL

This signal is reserved for future use and should be set LOW

during normal operation.

FACLPBK

Facility Loop Back

<1MHz

TTL

If this signal is set HIGH, all serial inputs are looped back to

their serial outputs. This will override the internal control

CMODE

Cell Mode

<1MHz

TTL

CMODE is set HIGH for Cell Mode operation.

TESTEN

Scan Test Enable

<1MHz

TTL

This signal is used in ATE testing to measure propagation

delay. It is also used in ATE testing of the BIST logic. Set to

logic LOW in normal operation.

SCANIN

Scan Data In

62.5Mb/s

TTL

The input signal for measuring propagation delay on the

ATE tester.

SCANOUT

Scan Data Out

62.5Mb/s

TTL

The output signal for measuring propagation delay on the

ATE tester. When TESTEN is set LOW, the longer delay

path is enabled.

WCLK

Word Clock

62.5MHz

TTL

This is the word clock output.

REFCLK

Reference Clock

62.5MHz

TTL

This is the reference clock and the source of the system wide

word clock period.

TCLKEN

Test Clock Enable

<1MHz

TTL

This input is set HIGH in test mode, so that the CMU is

bypassed and the REFCLK becomes the bit clock. This

signal is for ATE test only. Set LOW in normal operation.

CCLK

Cell Clock

62.5MHz

TTL

This is the source of the system wide cell clock. It is

internally synchronized to the REFCLK. In Packet mode, set

this signal HIGH to enable external switch configuration for

BIST.

RESET

Reset

<1MHz

TTL

Global chip reset (active LOW)

BSTLPBK

Built-in Self Test Loop

Back

<1MHz

TTL

When BSTLPBK is set HIGH and TESTEN is LOW, all

serial data output signals are looped back to their serial data

inputs. If BSTLPBK is set HIGH and TESTEN is HIGH,

only ports 0-7 are placed in loopback.

BSTEN

Built-in Self Test Enable

<1MHz

TTL

When BSTEN is HIGH, at-speed built-in self testing is

enabled.

BSTRST

Built-in Self Test Reset

<1MHz

TTL

The BSTRST signal is set HIGH to reset the PRBS

generator and comparator.

BSTPASS

Built-in Self Test Pass

<1MHz

TTL

The BSTPASS signal is HIGH if BTSEN is HIGH and the

PRBS comparator detects the correct pattern in built-in self

test mode.

Name

I/O

Freq

Type

Description

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