VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC880

High Performance 16x16

Serial Crosspoint Switch

G52191-0, Rev 4.2

Page 9

01/05/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Where:

CE Cell clock errorRCE

Resynch on cell errorICE

Interrupt on cell error

DE DRU error RDE

Resynch on DRU errorIDE

Interrupt on DRU error

TE

Threshold errorRTE

Resynch on thresh errorITE

Interrupt on threshold error

LE

Link error RLE

Resynch on link errorILE

Interrupt on link error

BIST

Set this bit HIGH to test the BIST circuitry

CDEL[3:0]

Cell clock delay

CERR[15:0]Cell clock error register, bit 0 is channel 0 etc, Cleared on read

DERR[15:0]DRU error register, bit 0 is channel 0 etc. Cleared on read

TERR[15:0]Threshold error register, bit 0 is channel 0 etc. Cleared on read

LERR[15:0]Link error register, bit 0 is channel 0 etc, Cleared on read

CN[3:0]Switch configuration data. N is the output port number, [3:0] is the input port connected. Default = 0xF.

SN[3:0]Output status data. N is the output port number, SN[3:2] = 00 for normal operation.

01 for out of synch

10 for word synch in progress

11 for cell synch in progress

SN[1] = Output busy in packet mode

SN[0] = Connection valid in packet mode

0 1 0 0 1 1

R/W

C7[3:0]

C15[3:0]

Output7/Output15 Config

1 0 1 1 0 0

R

S0[3:0]

S8[3:0]

Output0/Output8 Status

1 0 1 1 0 1

R

S1[3:0]

S9[3:0]

Output1/Output9 Status

1 0 1 1 1 0

R

S2[3:0]

S10[3:0]

Output2/Output10 Status

1 0 1 1 1 1

R

S3[3:0]

S11[3:0]

Output3/Output11 Status

1 1 0 0 0 0

R

S4[3:0]

S12[3:0]

Output4/Output12 Status

1 1 0 0 0 1

R

S5[3:0]

S13[3:0]

Output5/Output13 Status

1 1 0 0 1 0

R

S6[3:0]

S14[3:0]

Output6/Output14 Status

1 1 0 0 1 1

R

S7[3:0]

S15[3:0]

Output7/Output15 Status

X 1 0 1 0 0

R/W

FI[7:0]

Force IDLEs LSB

X 1 0 1 0 1

R/W

FI[15:8]

Force IDLEs MSB

X 1 0 1 1 0

R/W

RSY[7:0]

Resynch LSB

X 1 0 1 1 1

R/W

RSY[15:8]

Resynch MSB

X 1 1 0 0 0

R/W

OE[7:0]

Output Enable LSB

X 1 1 0 0 1

R/W

OE[15:8]

Output Enable MSB

X 1 1 0 1 0

R/W

LPBK[7:0]

Loopback LSB

X 1 1 0 1 1

R/W

LPBK[15:8]

Loopback MSB

CDATA[7:0] Bit Position

ADDR[5:0]

R/W

7

6

5

4

32

10