VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC880

High Performance 16x16

Serial Crosspoint Switch

Page 12

G52191-0, Rev 4.2

01/05/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Figure 5: Built-in Self-Test Functional Timing

The signal BSTRST is used to reset the PRBS pattern, and there is a comparator that sets the signal

BSTPASS HIGH if the test was successful. The functional timing diagram above shows a typical test sequence.

The PRBS pattern generator can also be tested by itself by setting the control register bit BIST HIGH. This

loops the output of the pattern generator directly back to the comparator circuit. This test will be typically run

before running the tests described above. In this case, the signals BSTEN, BSTRST and BSTPASS will operate

as shown in the Figure 5 above.

The BIST test can be run on no more than two ports at a time, for example: port 0

REFCLK

ADDR[4:0]

BSTRST

BSTPASS

< 10