DSPIC30F2011 datasheet(92/207 Pages) MICROCHIP

92 / 207 page

dsPIC30F2011/2012/3012/3013

DS70139C-page 90

Preliminary

Figure 13-2 depicts the a master/slave connection

between two processors. In Master mode, the clock is

generated by prescaling the system clock. Data is

transmitted as soon as a value is written to SPI1BUF.

The interrupt is generated at the middle of the transfer

of the last bit.

In Slave mode, data is transmitted and received as

external clock pulses appear on SCK. Again, the inter-

rupt is generated when the last bit is latched. If SS1

control is enabled, then transmission and reception are

enabled only when SS1 = low. The SDO1 output will be

disabled in SS1 mode with SS1 high.

The clock provided to the module is (FOSC/4). This

clock is then prescaled by the primary (PPRE<1:0>)

and the secondary (SPRE<2:0>) prescale factors. The

CKE bit determines whether transmit occurs on transi-

tion from active clock state to Idle clock state, or vice

versa. The CKP bit selects the Idle state (high or low)

for the clock.

13.1.1

WORD AND BYTE

COMMUNICATION

A control bit, MODE16 (SPI1CON<10>), allows the

module to communicate in either 16-bit or 8-bit mode.

16-bit operation is identical to 8-bit operation except

that the number of bits transmitted is 16 instead of 8.

The user software must disable the module prior to

changing the MODE16 bit. The SPI module is reset

when the MODE16 bit is changed by the user.

A basic difference between 8-bit and 16-bit operation is

that the data is transmitted out of bit 7 of the SPI1SR

for 8-bit operation, and data is transmitted out of bit15

of the SPI1SR for 16-bit operation. In both modes, data

is shifted into bit 0 of the SPI1SR.

13.1.2

SDO1 DISABLE

A control bit, DISSDO, is provided to the SPI1CON reg-

ister to allow the SDO1 output to be disabled. This will

allow the SPI module to be connected in an input only

configuration. SDO1 can also be used for general

purpose I/O.

13.2

Framed SPI Support

The module supports a basic framed SPI protocol in

Master or Slave mode. The control bit FRMEN enables

framed SPI support and causes the SS1 pin to perform

the frame synchronization pulse (FSYNC) function.

The control bit SPIFSD determines whether the SS1

pin is an input or an output (i.e., whether the module

receives or generates the frame synchronization

pulse). The frame pulse is an active high pulse for a

single SPI clock cycle. When frame synchronization is

enabled, the data transmission starts only on the

subsequent transmit edge of the SPI clock.

FIGURE 13-2:

SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SPI1BUF)

Shift Register

(SPI1SR)

MSb

LSb

SDO1

SDI1

PROCESSOR 1

SCK1

SPI™ Master

Serial Input Buffer

(SPI1BUF)

Shift Register

(SPI1SR)

LSb

MSb

SDI1

SDO1

PROCESSOR 2

SCK1

SPI™ Slave

Serial Clock

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